Datasheet

Datasheet, Volume 2 85
Processor Configuration Registers
11 RO-FW 0b Reserved (RSVD)
10:8 RO-FW 000b Reserved (RSVD)
7RO-FW 0b Reserved (RSVD)
6:4 RO-FW 000b Uncore
DDR3 Maximum Frequency Capability (DMFC)
PCODE will update this field with the value of FUSE_DMFC,
and then apply SSKU overrides.
Maximum allowed memory frequency with 133 MHz reference
clock.
This is a reversed 3-bit field:
7 = Up to DDR-1066 (4 x 266)
6 = Up to DDR-1333 (5 x 266)
5 = Up to DDR-1600 (6 x 266)
4 = Up to DDR-1866 (7 x 266)
3 = Up to DDR-2133 (8 x 266)
2 = Up to DDR-2400 (9 x 266)
1 = Up to DDR-2666 (10 x 266)
0 = Up to DDR-2933 (11 x 266) -- reserved fuse value; not
really supported;
3RO-FW 0b Reserved (RSVD)
2RO-FW 0b Reserved (RSVD)
1RO-FW 0b Reserved (RSVD)
0RO-FW 0b Reserved (RSVD)
B/D/F/Type: 0/0/0/PCI
Address Offset: E8-EBh
Default Value: 00100000h
Access: RO-FW, RO-KFW
Size: 32 bits
BIOS Optimal Default: 000000h
Bit Access Reset Value
RST/
PWR
Description