Datasheet

Datasheet, Volume 2 83
Processor Configuration Registers
2RO-FW0bUncore
IA Overclocking Enabled by DSKU
(OC_ENABLED_DSKU)
The default constant (non-fuse) value is zero. When the VDM
sets this bit, OC will be applied if OC_CTL_SSKU points to
DSKU.
1RO-FW0bUncore
On-die DDR write Vref generation allowed
(DDR_WRTVREF)
This bit allow on-die DDR write Vref generation.
PCODE will update this field with the value of
FUSE_DDR_WRTVREF.
0RO-FW0bUncore
DDR3L (1.35V DDR) operation allowed (DDR3L_EN)
This bit allows DDR3L (1.35V DDR) operation.
PCODE will update this field with the value of
FUSE_DDR3L_EN.
B/D/F/Type: 0/0/0/PCI
Address Offset: E4–E7h
Reset Value: 00000000h
Access: RO-FW, RO-KFW
Size: 32 bits
BIOS Optimal Default: 000000h
Bit Access
Reset
Value
RST/
PWR
Description