Datasheet

Processor Configuration Registers
82 Datasheet, Volume 2
2.5.38 CAPID0_A—Capabilities A Register
This register control of bits in this register are only required for customer visible SKU
differentiation.
B/D/F/Type: 0/0/0/PCI
Address Offset: E4–E7h
Reset Value: 00000000h
Access: RO-FW, RO-KFW
Size: 32 bits
BIOS Optimal Default: 000000h
Bit Access
Reset
Value
RST/
PWR
Description
31 RO-KFW 0b Reserved (RSVD)
30 RO-KFW 0b Reserved (RSVD)
29 RO-KFW 0b Reserved (RSVD)
28 RO-KFW 0b Reserved (RSVD)
27 RO-FW 0b Reserved (RSVD)
26 RO-FW 0b Reserved (RSVD)
25 RO-FW 0b Uncore Reserved
24 RO-FW 0b Reserved (RSVD)
23 RO-KFW 0b Uncore
VTd Disable (VTDD)
0 = Enable VTd
1 = Disable VTd
22 RO-FW 0b Reserved (RSVD)
21 RO-FW 0b Reserved (RSVD)
20:19 RO-FW 00b Reserved (RSVD)
18 RO-FW 0b Reserved (RSVD)
17 RO-FW 0b Reserved (RSVD)
16 RO-FW 0b Reserved (RSVD)
15 RO-KFW 0b Reserved (RSVD)
14 RO-FW 0b Uncore
2 DIMMS per Channel Disable (DDPCD)
This bit allows Dual Channel operation but only supports 1
DIMM per channel.
0 = 2 DIMMs per channel enabled
1 = 2 DIMMs per channel disabled. This setting hardwires
bits 2 and 3 of the rank population field for each channel
to zero. (MCHBAR offset 260h, bits 22:23 for channel 0
and MCHBAR offset 660h, bits 22:23 for channel 1)
13 RO-FW 0b Reserved (RSVD)
12 RO-FW 0b Reserved (RSVD)
11 RO-KFW 0b Reserved (RSVD)
10 RO-FW 0b Reserved (RSVD)
9:8 RO-FW 00b Reserved (RSVD)
7:4 RO-FW 0h Reserved (RSVD)