Datasheet

Datasheet, Volume 2 7
2.10.44 RCTL—Root Control Register............................................................... 202
2.10.45 LCAP2—Link Capabilities 2 Register ..................................................... 202
2.11 PCI Device 6 Extended Configuration Registers.................................................... 203
2.11.1 PVCCAP1—Port VC Capability Register 1 ............................................... 204
2.11.2 PVCCAP2—Port VC Capability Register 2 ............................................... 204
2.11.3 PVCCTL—Port VC Control Register ....................................................... 205
2.11.4 VC0RCAP—VC0 Resource Capability Register......................................... 205
2.11.5 VC0RCTL—VC0 Resource Control Register............................................. 207
2.11.6 VC0RSTS—VC0 Resource Status Register ............................................. 208
2.11.7 RCLDECH—Root Complex Link Declaration Enhanced ............................. 208
2.11.8 ESD—Element Self Description Register................................................ 209
2.11.9 LE1D—Link Entry 1 Description Register ............................................... 210
2.11.10 LE1A—Link Entry 1 Address Register.................................................... 210
2.11.11 LE1AH—Link Entry 1 Address Register.................................................. 211
2.11.12 APICBASE—APIC Base Address Register ............................................... 211
2.11.13 APICLIMIT—APIC Base Address Limit Register....................................... 212
2.11.14 CMNRXERR—Common Rx Error Register............................................... 212
2.11.15 PEGTST—PCI Express* Test Modes Register.......................................... 213
2.11.16 PEGUPDNCFG—PEG UPconfig/DNconfig Control Register ......................... 213
2.11.17 BGFCTL3—BGF Control 3 Register ....................................................... 214
2.11.18 EQPRESET1_2—Equalization Preset 1/2 Register ................................... 215
2.11.19 EQPRESET2_3_4—Equalization Preset 2/3/4 Register ............................. 215
2.11.20 EQPRESET6_7—Equalization Preset 6/7 Register ................................... 216
2.11.21 EQCFG—Equalization Configuration Register ......................................... 216
2.12 Direct Media Interface Base Address Registers (DMIBAR)...................................... 217
2.12.1 DMIVCECH—DMI Virtual Channel Enhanced Capability Register ............... 218
2.12.2 DMIPVCCAP1—DMI Port VC Capability Register 1................................... 219
2.12.3 DMIPVCCAP2—DMI Port VC Capability Register 2................................... 219
2.12.4 DMIPVCCTL—DMI Port VC Control Register ........................................... 220
2.12.5 DMIVC0RCAP—DMI VC0 Resource Capability Register ............................ 220
2.12.6 DMIVC0RCTL—DMI VC0 Resource Control Register ................................ 221
2.12.7 DMIVC0RSTS—DMI VC0 Resource Status Register ................................. 222
2.12.8 DMIVC1RCAP—DMI VC1 Resource Capability Register ............................ 222
2.12.9 DMIVC1RCTL—DMI VC1 Resource Control Register ................................ 223
2.12.10 DMIVC1RSTS—DMI VC1 Resource Status Register ................................. 224
2.12.11 DMIVCPRCAP—DMI VCp Resource Capability Register............................. 224
2.12.12 DMIVCPRCTL—DMI VCp Resource Control Register ................................ 225
2.12.13 DMIVCPRSTS—DMI VCp Resource Status Register ................................. 226
2.12.14 DMIVCMRCAP—DMI VCm Resource Capability Register ........................... 226
2.12.15 DMIVCMRCTL—DMI VCm Resource Control Register ............................... 227
2.12.16 DMIVCMRSTS—DMI VCm Resource Status Register................................ 228
2.12.17 DMIRCLDECH—DMI Root Complex Link Declaration Register ................... 228
2.12.18 DMIESD—DMI Element Self Description Register ................................... 229
2.12.19 DMILE1D—DMI Link Entry 1 Description Register................................... 230
2.12.20 DMILE1A—DMI Link Entry 1 Address Register........................................ 231
2.12.21 DMILUE1A—DMI Link Upper Entry 1 Address Register ............................ 231
2.12.22 DMILE2D—DMI Link Entry 2 Description Register................................... 232
2.12.23 DMILE2A—DMI Link Entry 2 Address Register........................................ 233
2.12.24 LCAP—Link Capabilities Register.......................................................... 233
2.12.25 LCTL—Link Control Register................................................................ 234
2.12.26 LSTS—DMI Link Status Register .......................................................... 235
2.12.27 LCTL2—Link Control 2 Register ........................................................... 236
2.12.28 LSTS2—Link Status 2 Register ............................................................ 238
2.13 MCHBAR Registers in Memory Controller—Channel 0 Registers .............................. 239
2.13.1 TC_DBP_C0—Timing of DDR – Bin Parameters Register .......................... 240
2.13.2 TC_RAP_C0—Timing of DDR – Regular Access Parameters Register.......... 241