Datasheet

Datasheet, Volume 2 61
Processor Configuration Registers
27 RW-V 0b Uncore
128 MB Base Address Mask (ADMSK128)
This bit is either part of the PCI Express Base Address (RW) or
part of the Address Mask (RO, read 0b), depending on the value
of bits 2:1 in this register.
26 RW-V 0b Uncore
64 MB Base Address Mask (ADMSK64)
This bit is either part of the PCI Express Base Address (RW) or
part of the Address Mask (RO, read 0b), depending on the value
of bits 2:1 in this register.
25:3 RO 0h Reserved (RSVD)
2:1 RW 00b Uncore
Length (LENGTH)
This field describes the length of this region.
00 = 256 MB (buses 0–255). Bits 38:28 are decoded in the PCI
Express Base Address Field.
01 = 128 MB (buses 0–127). Bits 38:27 are decoded in the PCI
Express Base Address Field.
10 = 64 MB (buses 0–63). Bits 38:26 are decoded in the PCI
Express Base Address Field.
11 = Reserved.
This register is locked by Intel TXT.
0RW 0bUncore
PCIEXBAR Enable (PCIEXBAREN)
0 = The PCIEXBAR register is disabled. Memory read and write
transactions proceed as if there were no PCIEXBAR register.
PCIEXBAR bits 38:26 are RW with no functionality behind
them.
1 = The PCIEXBAR register is enabled. Memory read and write
transactions whose address bits 38:26 match PCIEXBAR will
be translated to configuration reads and writes within the
Uncore. These Translated cycles are routed as shown in the
above table.
This register is locked by Intel TXT.
B/D/F/Type: 0/0/0/PCI
Address Offset: 60–67h
Reset Value: 0000000000000000h
Access: RW, RW-V
Size: 64 bits
BIOS Optimal Default 000000000000h
Bit Access
Reset
Value
RST/
PWR
Description