Datasheet

Processor Configuration Registers
338 Datasheet, Volume 2
2.21.25 IEADDR_REG—Invalidation Event Address Register
This register specifies the Invalidation Event Interrupt message address.
This register is treated as RsvdZ by implementations reporting Queued Invalidation
(QI) as not supported in the Extended Capability register.
2.21.26 IEUADDR_REG—Invalidation Event Upper Address
Register
This register specifies the Invalidation Event interrupt message upper address.
B/D/F/Type: 0/0/0/VC0PREMAP
Address Offset: A8–ABh
Reset Value: 00000000h
Access: RW-L
Size: 32 bits
BIOS Optimal Default 0h
Bit Access
Reset
Value
RST/
PWR
Description
31:2 RW-L 00000000h Uncore
Message address (MA)
When fault events are enabled, the contents of this register
specify the DWord-aligned address (bits 31:2) for the interrupt
request.
1:0 RO 0h Reserved (RSVD)
B/D/F/Type: 0/0/0/VC0PREMAP
Address Offset: AC–AFh
Reset Value: 00000000h
Access: RW-L
Size: 32 bits
Bit Access
Reset
Value
RST/
PWR
Description
31:0 RW-L 00000000h Uncore
Message Upper Address (MUA)
Hardware implementations supporting Queued Invalidations and
Extended Interrupt Mode are required to implement this register.
Hardware implementations not supporting Queued Invalidations
or Extended Interrupt Mode may treat this field as RsvdZ.