Datasheet

Processor Configuration Registers
308 Datasheet, Volume 2
2.20 PXPEPBAR Registers
2.20.1 EPVC0RCTL—EP VC 0 Resource Control Register
This register controls the resources associated with Egress Port Virtual Channel 0.
Table 2-23. PXPEPBAR Address Map
Address
Offset
Register Symbol Register Name Reset Value Access
0–13h RSVD Reserved 0h RO
14–17h EPVC0RCTL EP VC 0 Resource Control 800000FFh RO, RW
18–9Fh RSVD Reserved — —
B/D/F/Type: 0/0/0/PXPEPBAR
Address Offset: 14–17h
Reset Value: 800000FFh
Access: RO, RW
Size: 32 bits
BIOS Optimal Default 00000h
Bit Access
Reset
Value
RST/
PWR
Description
31:20 RO 0h Reserved (RSVD)
19:17 RW 000b Uncore
Port Arbitration Select (PAS)
This field configures the VC resource to provide a particular Port
Arbitration service. The value of 0h corresponds to the bit
position of the only asserted bit in the Port Arbitration Capability
field.
16:0 RO 0h Reserved (RSVD)