Datasheet

Datasheet, Volume 2 299
Processor Configuration Registers
2.19.3 MEM_TRML_STATUS_REPORT—Memory Thermal
Status Report Register
This register reports the thermal status of DRAM.
B/D/F/Type: 0/0/0/MCHBAR PCU
Address Offset: 58A0–58A3h
Reset Value: 00000000h
Access: RO-V
Size: 32 bits
BIOS Optimal Default 00h
Bit Access
Reset
Value
RST/
PWR
Description
31:25 RO 0h Reserved (RSVD)
24 RO-V 0b Uncore
Double Self refresh (DSR)
0 = Normal self refresh
1 = Double self refresh
23:16 RO-V 00h Uncore Reserved (RSVD)
15:8 RO-V 00h Uncore
Channel 1 Status (CHANNEL1_STATUS)
The format is for each channel and is defined as follows:
00 = Cold
01 = Warm
11 = Hot
Bits 8:9: Rank 0 Channel 1
Bits 10:11: Rank 1 Channel 1
Bits 12:13: Rank 2 Channel 1
Bits 14:15: Rank 3 Channel 1
7:0 RO-V 00h Uncore
Channel 0 Status (CHANNEL0_STATUS)
The format is for each channel and is defined as follows:
00 = Cold
01 = Warm
11 = Hot
Bits 0:1: Rank 0 Channel 0
Bits 2:3: Rank 1 Channel 0
Bits 4:5: Rank 2 Channel 0
Bits 6:7: Rank 3 Channel 0