Datasheet

Datasheet, Volume 2 261
Processor Configuration Registers
2.18.1 VER_REG—Version Register
This register reports the architecture version supported. Backward compatibility for the
architecture is maintained with new revision numbers, allowing software to load
remapping hardware drivers written for prior architecture versions.
AC–AFh IEUADDR_REG
Invalidation Event Upper Address
Register
00000000h RW-L
B0–B7h RSVD Reserved 0h RO
B8–BFh IRTA_REG
Interrupt Remapping Table Address
Register
000000000
0000000h
RW-L
C0–FFh RSVD Reserved 0h RO
100–107h IVA_REG
Invalidate Address Register 000000000
0000000h
RW
108–10Fh IOTLB_REG
IOTLB Invalidate Register 020000000
0000000h
RO-V, RW,
RW-V
110–1FFh RSVD Reserved 0h RO
200–207h FRCDL_REG
Fault Recording Low Register 000000000
0000000h
ROS-V
208–20Fh FRCDH_REG
Fault Recording High Register 0000000000
000000h
RO, RW1CS,
ROS-V
210–FEFh RSVD Reserved 0h RO
FF0–FF3h VTPOLICY
DMA Remap Engine Policy Control
00000000h
RW-L, RO, RO-
KFW, RW-KL
Table 2-21. Integrated Graphics VTd Remapping Engine Register Address Map (Sheet 2 of
2)
Address
Offset
Register Symbol Register Name Reset Value Access
B/D/F/Type: 0/0/0/GFXVTBAR
Address Offset: 0–3h
Reset Value: 00000010h
Access: RO
Size: 32 bits
BIOS Optimal Default 000000h
Bit Access
Reset
Value
RST/
PWR
Description
31:8 RO 0h Reserved (RSVD)
7:4 RO 0001b Uncore
Major Version number (MAX)
Indicates supported architecture version.
3:0 RO 0000b Uncore
Minor Version number (MIN)
Indicates supported architecture minor version.