Datasheet

Processor Configuration Registers
26 Datasheet, Volume 2
2.3.3.1 APIC Configuration Space (FEC0_0000h – FECF_FFFFh)
This range is reserved for APIC configuration space. The I/O APIC(s) usually reside in
the PCH portion of the chipset, but may also exist as stand-alone components like PXH.
The IOAPIC spaces are used to communicate with IOAPIC interrupt controllers that
may be populated in the system. Since it is difficult to relocate an interrupt controller
using plug-and-play software, fixed address decode regions have been allocated for
them. Processor accesses to the default IOAPIC region (FEC0_0000h to FEC7_FFFFh)
are always forwarded to DMI.
The processor optionally supports additional I/O APICs behind the PCI Express
“Graphics” port. When enabled using the APIC_BASE and APIC_LIMIT registers
(mapped PCI Express Configuration space offset 240h and 244h), the PCI Express
port(s) will positively decode a subset of the APIC configuration space.
Figure 2-4. PCI Memory Address Range
DMI Interface
(subtractive decode)
FEF0_0000h
4 GB – 2 MB
MSI Interrupts
FEE0_0000h
PCI Express* Configuration
Space
E000_0000h
High BIOS
FFE0_0000h
FFFF_FFFFh
4 GB
4 GB – 17 MB
DMI Interface
(subtractive decode)
FED0_0000h
4 GB – 18 MB
Local (CPU) APIC
FEC8_0000h
4 GB – 19 MB
I/O APIC
FEC0_0000h 4 GB – 20 MB
DMI Interface
(subtractive decode)
F000_0000h
4 GB – 256 MB
Possible
address range/
size (not
ensured)
4 GB – 512 MB
DMI Interface
(subtractive decode)
TOLUD
BARs, Internal
Graphics
ranges, PCI
Express* Port,
CHAPADR could
be here.