Datasheet

Datasheet, Volume 2 259
Processor Configuration Registers
2.17.2 PM_CMD_PWR—Power Management Command Power
Register
This register defines the power contribution of each command – ACT+PRE, CAS-read,
and CAS write. Assumption is that the ACT is always followed by a PRE (although not
immediately), and REF commands are issued in a fixed rate and there is no need to
count them. The register has 3 8-bit fields.
2.17.3 PM_BW_LIMIT_CONFIG—BW Limit Configuration Register
This register defines the BW throttling at temperature.
Note: The field “BW_limit_tf may not be changed in run-time. Other fields may be changed in
run-time.
B/D/F/Type: 0/0/0/MCHBAR_MCBCAST
Address Offset: 4F84–4F87h
Reset Value: 00000000h
Access: RW-LV
Size: 32 bits
BIOS Optimal Default 00h
Bit Access
Reset
Value
RST/
PWR
Description
31:24 RO 0h Reserved (RSVD)
23:16 RW-LV 00h Uncore Power contribution of CAS Write command (PWR_CAS_W)
15:8 RW-LV 00h Uncore Power contribution of CAS Read command (PWR_CAS_R)
7:0 RW-LV 00h Uncore
Power contribution of RAS command and PRE command
(PWR_RAS_PRE)
Power contribution of RAS command and PRE command. The
value should be the sum of the two commands, assuming that
each RAS command for a given page is followed by a PRE
command to the same page in the near future.
B/D/F/Type: 0/0/0/MCHBAR_MCBCAST
Address Offset: 4F88–4F8Bh
Reset Value: FFFF03FFh
Access: RW-L
Size: 32 bits
BIOS Optimal Default 5F7003FFh
Bit Access
Reset
Value
RST/
PWR
Description
31:24 RW-L FFh Uncore
BW limit when rank is hot (BW_limit_hot)
Number of transactions allowed per rank when status of rank is
hot. Range: 0–255h
23:16 RW-L FFh Uncore
BW limit when rank is warm (BW_limit_warm)
Number of transactions allowed per rank when status of rank is
warm. Range: 0–255h
15:10 RO 0h Reserved (RSVD)
9:0 RW-L 3FFh Uncore
BW limit time frame (BW_limit_tf)
Time frame in which the BW limit is enforced, in DCLK cycles.
Range: 1–1023h
Note: The field “BW_limit_tf may not be changed in run-time.