Datasheet

Processor Configuration Registers
256 Datasheet, Volume 2
2.16.4 PM_SREF_config—Self Refresh Configuration Register
This is a self refresh mode control register – defines if and when DDR can go into SR.
B/D/F/Type: 0/0/0/MCHBAR_MCMAIN
Address Offset: 5060–5063h
Reset Value: 000100FFh
Access: RW-L
Size: 32 bits
BIOS Optimal Default 0000h
Bit Access
Reset
Value
RST/
PWR
Description
31:16 RO 0h Reserved (RSVD)
15:0 RW-L 00FFh Uncore
Idle timer init value (Idle_timer)
This value is used when the “SREF_enable” field is set. It defines
the number of cycles that there should not be any transaction in
order to enter self-refresh. It is programmable 1 to 64K-1. In
DCLK=800 it determines time of up to 82 us.