Datasheet

Datasheet, Volume 2 247
Processor Configuration Registers
2.14.3 SC_IO_LATENCY_C1—IO Latency configuration Register
This register identifies the I/O latency per rank, and I/O compensation (global).
15:12 RW-L 4h Uncore
tWTR in DCLK cycles (tWTR)
Delay from internal WR transaction to internal RD transaction.
The minimum delay is 4 DCLK cycles, whereas the maximum
delay is 8 DCLK cycles.
11:8 RW-L 3h Uncore
tCKE in DCLK cycles (tCKE)
CKE minimum pulse width in DCLK cycles. The minimum value is
3 DCLK cycles, whereas the maximum value is the actual value of
tXP.
7:4 RW-L 4h Uncore
tRTP in DCLK cycles (tRTP)
Minimum delay from CAS-RD to PRE. The minimum delay is 4
DCLK cycles, whereas the maximum delay is 8 DCLK cycles.
3:0 RW-L 4h Uncore
tRRD in DCLK cycles (tRRD)
tRRD is the minimum delay between two ACT commands
targeted to different banks in the same rank. The minimum delay
is 4 DCLK cycles, whereas the maximum delay is 7 cycles.
B/D/F/Type: 0/0/0/MCHBAR MC1
Address Offset: 4404–4407h
Reset Value: 86104344h
Access: RW-L
Size: 32 bits
Bit Access
Reset
Value
RST/
PWR
Description
B/D/F/Type: 0/0/0/MCHBAR MC1
Address Offset: 4428–442Bh
Reset Value: 000E0000h
Access: RW-L
Size: 32 bits
BIOS Optimal Default 00h
Bit Access
Reset
Value
RST/
PWR
Description
31:22 RO 0h Reserved (RSVD)
21:16 RW-L 0Eh Uncore Round trip – I/O compensation (RT_IOCOMP)
15:12 RW-L 0h Uncore IO latency Rank 1 DIMM 1 (IOLAT_R1D1)
11:8 RW-L 0h Uncore IO latency Rank 0 DIMM 1 (IOLAT_R0D1)
7:4 RW-L 0h Uncore IO latency Rank 1 DIMM 0 (IOLAT_R1D0)
3:0 RW-L 0h Uncore IO latency Rank 0 DIMM 0 (IOLAT_R0D0)