Datasheet

Datasheet, Volume 2 239

Processor Configuration Registers

2.13 MCHBAR Registers in Memory Controller—Channel

0 Registers

Table 2-16. MCHBAR Registers in Memory Controller – Channel 0 Register Address Map

Address

Offset

Symbol

0–3FFFh RSVD Reserved 0h RO

4000–4003h TC_DBP_C0 Timing of DDR – bin parameters 00146666h RW-L

4004–4007h TC_RAP_C0 Timing of DDR – regular access parameters 86104344h RW-L

4008–4027h RSVD Reserved — —

4028–402Bh

SC_IO_LATE

NCY_C0

IO Latency configuration

000E0000h RW-L

402C–409Fh RSVD Reserved — —

40A0–40A3h

PM_PDWN_c

onfig_C0

Power-down configuration register

00000000h RW-L

40A4–40B3h RSVD Reserved — —

40BC–40C7h RSVD Reserved 0h RO

40D0–4293h RSVD Reserved — —

4294–4297h TC_RFP_C0 Refresh Parameters 0000980Fh RW-L

4298–429Bh TC_RFTP_C0 Refresh Timing Parameters 46B41004h RW-L

429C–438Fh RSVD Reserved — —