Datasheet

Datasheet, Volume 2 237
Processor Configuration Registers
9:7 RWS-V 000b Powergood
Transmit Margin (txmargin)
This field controls the value of the non-deemphasized voltage
level at the Transmitter pins. This field is reset to 000b on
entry to the LTSSM Polling.Configuration substate (see PCIe
Specification, Chapter 4 for details of how the transmitter
voltage level is determined in various states).
000 = Normal operating range
001 = 800–1200 mV for full swing and 400–700 mV
for half-swing
010 – (n-1) = Values must be monotonic with a non-zero
slope. The value of n must be greater than 3
and less than 7.
At least two of these must be below the
normal operating range
n = 200–400 mV for full-swing and 100–200 mV
for half-swing
n–111 = Reserved
Reset Value is 000b.
Components that support only the 2.5 GT/s speed are
permitted to hardwire this bit to 0b.
When operating in 5 GT/s mode with full swing, the de-
emphasis ratio must be maintained within ±1 dB from the
specification defined operational value (either -3.5 or -6 dB).
The processor supports the following values:
000 = Normal operation (Reset Value); coefficients (cursor,
precursor, postcursor) are at defined values
001 = Coefficients are divided by 2
010 = Coefficients are divided by 4
011 = Coefficients are divided by 8
All other codes are reserved.
The coefficients translate to 4 "level" values that are sent to
the AFE. Note that Tx margining has no effect on the levels if
"bypass levels" are enabled.
6RWS 0bPowergood
Selectable De-emphasis (selectabledeemphasis)
When the Link is operating at 5 GT/s speed, selects the level of
de-emphasis. Encodings:
1b = -3.5 dB
0b = -6 dB
When the Link is operating at 2.5 GT/s speed, the setting of
this bit has no effect. Components that support only the
2.5 GT/s speed are permitted to hardwire this bit to 0b.
NOTE: For DMI this bit has no effect in functional mode as DMI
is half-swing and will use -3.5 dB whenever de-emphasis is
enabled.
B/D/F/Type: 0/0/0/DMIBAR
Address Offset: 98–99h
Reset Value: 0002h
Access: RWS, RWS-V
Size: 16 bits
Bit Access
Reset
Value
RST/
PWR
Description