Datasheet

Datasheet, Volume 2 235
Processor Configuration Registers
2.12.26 LSTS—DMI Link Status Register
This register indicates DMI status.
4RW 0bUncore
Link Disable (LD)
0 = Normal operation
1 = link is disabled. Forces the LTSSM to transition to the
Disabled state (using Recovery) from L0, L0s, or L1 states.
Link retraining happens automatically on 0 to 1 transition,
just like when coming out of reset.
Writes to this bit are immediately reflected in the value read from
the bit, regardless of actual Link state.
After clearing this bit, software must honor timing requirements
defined in Section 6.6.1 with respect to the first Configuration
Read following a Conventional Reset.
3RO 0bUncore
Read Completion Boundary (RCB)
Hardwired to 0 to indicate 64 byte.
2RO 0h Reserved (RSVD)
1:0 RW 00b Uncore
Active State PM (ASPM)
This field controls the level of active state power management
supported on the given link.
00 = Disabled
01 = L0s Entry Supported
10 = Reserved
11 = L0s and L1 Entry Supported
B/D/F/Type: 0/0/0/DMIBAR
Address Offset: 88–89h
Reset Value: 0000h
Access: RW, RW-V
Size: 16 bits
BIOS Optimal Default 000h
Bit Access
Reset
Value
RST/
PWR
Description
B/D/F/Type: 0/0/0/DMIBAR
Address Offset: 8A–8Bh
Reset Value: 0001h
Access: RO-V
Size: 16 bits
BIOS Optimal Default 00h
Bit Access
Reset
Value
RST/
PWR
Description
15:12 RO 0h Reserved (RSVD)
11 RO-V 0b Uncore
Link Training (LTRN)
This field indicates that the Physical Layer LTSSM is in the
Configuration or Recovery state, or that 1b was written to the
Retrain Link bit but Link training has not yet begun. Hardware
clears this bit when the LTSSM exits the Configuration/Recovery
state once Link training is complete.
10:0 RO 0h Reserved (RSVD)