Datasheet

Datasheet, Volume 2 231
Processor Configuration Registers
2.12.20 DMILE1A—DMI Link Entry 1 Address Register
This register provides the second part of a Link Entry that declares an internal link to
another Root Complex Element.
2.12.21 DMILUE1A—DMI Link Upper Entry 1 Address Register
This register provides the second part of a Link Entry that declares an internal link to
another Root Complex Element.
B/D/F/Type: 0/0/0/DMIBAR
Address Offset: 58–5Bh
Reset Value: 00000000h
Access: RW-O
Size: 32 bits
BIOS Optimal Default 000h
Bit Access
Reset
Value
RST/
PWR
Description
31:12 RW-O 00000h Uncore
Link Address (LA)
Memory mapped base address of the RCRB that is the target
element (egress port of PCH) for this link entry.
11:0 RO 0h Reserved (RSVD)
B/D/F/Type: 0/0/0/DMIBAR
Address Offset: 5C–5Fh
Reset Value: 00000000h
Access: RW-O
Size: 32 bits
BIOS Optimal Default 000000h
Bit Access
Reset
Value
RST/
PWR
Description
31:8 RO 0h Reserved (RSVD)
7:0 RW-O 00h Uncore
Upper Link Address (ULA)
Memory mapped base address of the RCRB that is the target
element (egress port of PCH) for this link entry.