Datasheet

Processor Configuration Registers
218 Datasheet, Volume 2
2.12.1 DMIVCECH—DMI Virtual Channel Enhanced Capability
Register
This register indicates DMI Virtual Channel capabilities.
8A–8Bh LSTS DMI Link Status 0001h RO-V
8C–97h RSVD Reserved 0h RO
98–99h LCTL2 Link Control 2 0002h RWS, RWS-V
9A–9Bh LSTS2 Link Status 2 0000h RO-V
9C–D33h RSVD Reserved 0h RO
D34–D37h RSVD Reserved 0000005Fh RW, RW1CS
Table 2-15. DMIBAR Register Address Map (Sheet 2 of 2)
Address
Offset
Register Symbol Register Name Reset Value Access
B/D/F/Type: 0/0/0/DMIBAR
Address Offset: 0–3h
Reset Value: 04010002h
Access: RO
Size: 32 bits
Bit Access
Reset
Value
RST/
PWR
Description
31:20 RO 040h Uncore
Pointer to Next Capability (PNC)
This field contains the offset to the next PCI Express capability
structure in the linked list of capabilities (Link Declaration
Capability).
19:16 RO 1h Uncore
PCI Express Virtual Channel Capability Version
(PCIEVCCV)
Hardwired to 1 to indicate compliances with the 1.1 version of
the PCI Express specification.
Note: This version does not change for 2.0 compliance.
15:0 RO 0002h Uncore
Extended Capability ID (ECID)
Value of 0002h identifies this linked list item (capability
structure) as being for PCI Express Virtual Channel registers.