Datasheet

Datasheet, Volume 2 217
Processor Configuration Registers
2.12 Direct Media Interface Base Address Registers
(DMIBAR)
Table 2-15. DMIBAR Register Address Map (Sheet 1 of 2)
Address
Offset
Register Symbol Register Name Reset Value Access
0–3h DMIVCECH DMI Virtual Channel Enhanced Capability 04010002h RO
4–7h DMIPVCCAP1 DMI Port VC Capability Register 1 00000000h RO, RW-O
8–Bh DMIPVCCAP2 DMI Port VC Capability Register 2 00000000h RO
C–Dh DMIPVCCTL DMI Port VC Control 0000h RW, RO
E–Fh RSVD Reserved 0h RO
10–13h DMIVC0RCAP DMI VC0 Resource Capability 00000001h RO
14–17h DMIVC0RCTL DMI VC0 Resour ce Control 8000007Fh RO, RW
18–19h RSVD Reserved 0h RO
1A–1Bh DMIVC0RSTS DMI VC0 Resource Status 0002h RO-V
1C–1Fh DMIVC1RCAP DMI VC1 Resource Capability 00008001h RO
20–23h DMIVC1RCTL DMI VC1 Resource Control 01000000h RO, RW
24–25h RSVD Reserved 0h RO
26–27h DMIVC1RSTS DMI VC1 Resource Status 0002h RO-V
28–2Bh DMIVCPRCAP DMI VCp Resource Capability 00000001h RO
2C–2Fh DMIVCPRCTL DMI VCp Resource Control 02000000h RO, RW
30–31h RSVD Reserved 0h RO
32–33h DMIVCPRSTS DMI VCp Resource Status 0002h RO-V
34–37h DMIVCMRCAP DMI VCm Resource Capability 00008000h RO
38–3Bh DMIVCMRCTL DMI VCm Resource Control 07000080h RW, RO
3C–3Dh RSVD Reserved 0h RO
3E–3Fh DMIVCMRSTS DMI VCm Resource Status 0002h RO-V
40–43h DMIRCLDECH DMI Root Complex Link Declaration 08010005h RO
44–47h DMIESD DMI Element Self Description 01000202h RO, RW-O
48–4Fh RSVD Reserved 0h RO
50–53h DMILE1D DMI Link Entry 1 Description 00000000h RW-O, RO
54–57h RSVD Reserved 0h RO
58–5Bh DMILE1A DMI Link Entry 1 Address 00000000h RW-O
5C–5Fh DMILUE1A DMI Link Upper Entry 1 Address 00000000h RW-O
60–63h DMILE2D DMI Link Entry 2 Description 00000000h RO, RW-O
64–67h RSVD Reserved 0h RO
68–6Bh DMILE2A DMI Link Entry 2 Address 00000000h RW-O
6C–6Fh RSVD Reserved 00000000h RW-O
70–7Fh RSVD Reserved 0h RO
80–83h RSVD Reserved 00010006h RO
84–87h LCAP
Link Capabilities
0001AC41h
RW-O, RO,
RW-OV
88–89h LCTL Link Control 0000h RW, RW-V