Datasheet

Processor Configuration Registers
216 Datasheet, Volume 2
2.11.20 EQPRESET6_7—Equalization Preset 6/7 Register
This register contains coefficients for Preset 6 and 7.
2.11.21 EQCFG—Equalization Configuration Register
B/D/F/Type: 0/6/0/MMR
Address Offset: DCC–DCFh
Reset Value: 36200E06h
Access: RW
Size: 32 bits
BIOS Optimal Default 0h
Bit Access
Reset
Value
RST/
PWR
Description
31:6 RO 0h Reserved (RSVD)
5:0 RW 06h Uncore
Preset 6 Precursor Coefficient (PRECUR6):
Precursor coefficient for Preset 6.
B/D/F/Type: 0/6/0/MMR
Address Offset: DD8–DDBh
Reset Value: 00000000h
Access: RW
Size: 32 bits
BIOS Optimal Default 00000000h
Bit Access
Reset
Value
RST/
PWR
Description
31:2 RO 0h Reserved (RSVD)
1RW 0 Uncore
Disable Margining (MARGINDIS)
When set, it will disable Tx margining during Polling.Compliance
and Recovery.
0RO 0 Reserved (RSVD)