Datasheet

Processor Configuration Registers
214 Datasheet, Volume 2
2.11.17 BGFCTL3—BGF Control 3 Register
B/D/F/Type: 0/6/0/MMR
Address Offset: D6C–D6Fh
Reset Value: 400204E0h
Access: RW
Size: 32 bits
BIOS Optimal Default 0000h
Bit Access
Reset
Value
RST/
PWR
Description
31 RW 0b Uncore
Fclock Bubble Enable (FBEN)
This bit disable Bubble generator on Fclk side of BGF.
0 = Disabled
1 = Enabled.
30 RW 1b Uncore
Lclock Bubble Enable (LBEN)
This bit enable Bubble generator on Lclk side of BGF
0 = Disabled
1 = Enabled.
Bubble generation is disabled on slow side
29:18 RO 0h Reserved (RSVD)
17:13 RW 10000b Uncore
Slow ratio for gen 3 (SRG3)
This field defines the BGF slow ration for gen3
12:8 RW 00100b Uncore
BGF Ratio delta for Gen 3 (RDG3)
This register defines the BGF Ratio delta for Gen 3. Delta
between the fast and slow clock multiplier
7:0 RO 0h Reserved (RSVD)