Datasheet

Processor Configuration Registers
212 Datasheet, Volume 2
2.11.13 APICLIMIT—APIC Base Address Limit Register
2.11.14 CMNRXERR—Common Rx Error Register
B/D/F/Type: 0/6/0/MMR
Address Offset: 244–247h
Reset Value: 00000000h
Access: RW
Size: 32 bits
BIOS Optimal Default 000000h
Bit Access
Reset
Value
RST/
PWR
Description
31:12 RO 0h Reserved (RSVD)
11:4 RW 00h Uncore
APIC Base Address (APICLIMIT):
Bits 19:12 of the APIC Limit
Bits 31:20 are assumed to be FECh. Bits 0:11 are don't care for
address decode.
Address decoding to the APIC range is done as:
APIC_BASE [31:12] ≤ A[31:12] ≤ APIC_LIMIT[31:12]
3:0 RO 0h Reserved (RSVD)
B/D/F/Type: 0/6/0/MMR
Address Offset: C34–C37h
Reset Value: 00000000h
Access: RW1CS
Size: 32 bits
BIOS Optimal Default 0000000h
Bit Access
Reset
Value
RST/
PWR
Description
31:3 RO 0h Reserved (RSVD)
2 RW1CS 0b Powergood
Gen1/2 UFD Framing Error Status (UFDFRAMEERR):
Only applicable for Gen1/Gen2. When set, this field indicates
that a framing error occurred in the Link. (that is, dropped STP,
dropped SDP, dropped END)
1:0 RO 0h Reserved (RSVD)