Datasheet

Datasheet, Volume 2 211
Processor Configuration Registers
2.11.11 LE1AH—Link Entry 1 Address Register
This register provides the second part of a Link Entry that declares an internal link to
another Root Complex Element.
2.11.12 APICBASE—APIC Base Address Register
B/D/F/Type: 0/6/0/MMR
Address Offset: 15C–15Fh
Reset Value: 00000000h
Access: RW-O
Size: 32 bits
BIOS Optimal Default 000000h
Bit Access
Reset
Value
RST/
PWR
Description
31:8 RO 0h Reserved (RSVD)
7:0 RW-O 00h Uncore
Link Address (LA)
Memory mapped base address of the RCRB that is the target
element (Egress Port) for this link entry.
BIOS Requirement: This field is inserted by BIOS such that it
matches PXPEPBAR.
B/D/F/Type: 0/6/0/MMR
Address Offset: 240–243h
Reset Value: 00000000h
Access: RW
Size: 32 bits
BIOS Optimal Default 000000h
Bit Access
Reset
Value
RST/
PWR
Description
31:12 RO 0h Reserved (RSVD)
11:4 RW 00h Uncore
APIC Base Address (APICBASE):
Bits 19:12 of the APIC Base
Bits 31:20 are assumed to be FECh. Bits 0:11 are don't care for
address decode.
Address decoding to the APIC range is done as:
APIC_BASE [31:12] ≤ A[31:12] ≤ APIC_LIMIT[31:12]
3:1 RO 0h Reserved (RSVD)
0RW 0bUncore
APIC Range Enable (APICRE):
Enables the decode of the APIC window.
0 = Disable
1 = Enable