Datasheet

Processor Configuration Registers
210 Datasheet, Volume 2
2.11.9 LE1D—Link Entry 1 Description Register
This register provides the first part of a Link Entry that declares an internal link to
another Root Complex Element.
2.11.10 LE1A—Link Entry 1 Address Register
This register provides the second part of a Link Entry that declares an internal link to
another Root Complex Element.
B/D/F/Type: 0/6/0/MMR
Address Offset: 150–153h
Reset Value: 00000000h
Access: RO, RW-O
Size: 32 bits
BIOS Optimal Default 0000h
Bit Access
Reset
Value
RST/
PWR
Description
31:24 RO 00h Uncore
Target Port Number (TPN)
Specifies the port number associated with the element targeted
by this link entry (Egress Port). The target port number is with
respect to the component that contains this element as specified
by the target component ID.
00h is the egress port (memory).
23:16 RW-O 00h Uncore
Target Component ID (TCID)
Identifies the physical or logical component that is targeted by
this link entry.
BIOS Requirement: This field must be initialized according to
guidelines in the PCI Express* Isochronous/Virtual Channel
Support Hardware Programming Specification (HPS).
15:2 RO 0h Reserved (RSVD)
1RO 0bUncore
Link Type (LTYP)
Indicates that the link points to memory-mapped space (for
RCRB). The link address specifies the 64-bit base address of the
target RCRB.
0RW-O 0b Uncore
Link Valid (LV)
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
BIOS should write "1' to this bit once it has programmed Link
Entry 1 Address (LE1A) and while it writes the TCID in this
register
B/D/F/Type: 0/6/0/MMR
Address Offset: 158–15Bh
Reset Value: 00000000h
Access: RW-O
Size: 32 bits
BIOS Optimal Default 000h
Bit Access
Reset
Value
RST/
PWR
Description
31:12 RW-O 00000h Uncore
Link Address (LA)
Memory mapped base address of the RCRB that is the target
element (Egress Port) for this link entry.
BIOS Requirement: This field is inserted by BIOS such that it
matches PXPEPBAR.
11:0 RO 0h Reserved (RSVD)