Datasheet

Processor Configuration Registers
204 Datasheet, Volume 2
2.11.1 PVCCAP1—Port VC Capability Register 1
This register describes the configuration of PCI Express* Virtual Channels associated
with this port.
2.11.2 PVCCAP2—Port VC Capability Register 2
This register describes the configuration of PCI Express* Virtual Channels associated
with this port.
B/D/F/Type: 0/6/0/MMR
Address Offset: 104–107h
Reset Value: 00000000h
Access: RO
Size: 32 bits
BIOS Optimal Default 0000000h
Bit Access
Reset
Value
RST/
PWR
Description
31:7 RO 0h Reserved (RSVD)
6:4 RO 000b Uncore
Low Priority Extended VC Count (LPEVCC)
Indicates the number of (extended) Virtual Channels in addition
to the default VC belonging to the low-priority VC (LPVC) group
that has the lowest priority with respect to other VC resources in
a strict-priority VC Arbitration. The value of 0 in this field implies
strict VC arbitration.
3RO 0h Reserved (RSVD)
2:0 RO 000b Uncore
Extended VC Count (EVCC)
Indicates the number of (extended) Virtual Channels in addition
to the default VC supported by the device.
B/D/F/Type: 0/6/0/MMR
Address Offset: 108–10Bh
Reset Value: 00000000h
Access: RO
Size: 32 bits
BIOS Optimal Default 0000h
Bit Access
Reset
Value
RST/
PWR
Description
31:24 RO 00h Uncore
VC Arbitration Table Offset (VCATO):
Indicates the location of the VC Arbitration Table. This field
contains the zero-based offset of the table in DQWORDS (16
bytes) from the base address of the Virtual Channel Capability
Structure. A value of 0 indicates that the table is not present
(due to fixed VC priority).
23:8 RO 0h Reserved (RSVD)
7:0 RO 00h Uncore Reserved for VC Arbitration Capability (VCAC):