Datasheet

Datasheet, Volume 2 159
Processor Configuration Registers
2.8.20 MAXLAT—Maximum Latency Register
The Integrated Graphics Device has no requirement for the settings of Latency Timers.
2.8.21 MSAC—Multi Size Aperture Control Register
This register determines the size of the graphics memory aperture in Function 0 and in
the trusted space. Only the system BIOS will write this register based on pre- boot
address allocation efforts, but the graphics may read this register to determine the
correct aperture size. System BIOS needs to save this value on boot so that it can reset
it correctly during S3 resume.
B/D/F/Type: 0/2/0/PCI
Address Offset: 3Fh
Reset Value: 00h
Access: RO
Size: 8 bits
Bit Access
Reset
Value
RST/
PWR
Description
7:0 RO 00h Uncore
Maximum Latency Value (MLV)
The IGD has no specific requirements for how often it needs to
access the PCI bus.
B/D/F/Type: 0/2/0/PCI
Address Offset: 62h
Reset Value: 02h
Access: RW, RW-K
Size: 8 bits
BIOS Optimal Default 0h
Bit Access
Reset
Value
RST/
PWR
Description
7:4 RW 0h Uncore
Reserved RW (RSVDRW)
Scratch Bits Only -- Have no physical effect on hardware
3RO 0h Reserved (RSVD)
2RW-K 0b Uncore
Untrusted Aperture Size High (LHSASH)
This field is used in conjunction with LHSASL. The description
below is for both fields (LHSASH & LHSASL).
11 = Bits [28:27] of GMADR are RO, allowing 512 MB of GMADR
10 = Illegal Programming
01 = Bit [28] of GMADR is RW but bit [27] of GMADR is RO,
allowing 256 MB of GMADR
00 = Bits [28:27] of GMADR are RW, allowing 128 MB of GMADR
1RW-K 1b Uncore
Untrusted Aperture Size Low (LHSASL)
This field is used in conjunction with LHSASH. The description
below is for both fields (LHSASH & LHSASL).
11 = Bits [28:27] of GMADR are RO, allowing 512 MB of GMADR
10 = Illegal Programming
01 = Bit [28] of GMADR is RW but bit [27] of GMADR is RO,
allowing 256 MB of GMADR
00 = Bits [28:27] of GMADR are RW, allowing 128 MB of GMADR
0RO 0h Reserved (RSVD)