Datasheet

Datasheet, Volume 2 151
Processor Configuration Registers
2.8.4 PCISTS2—PCI Status Register
PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master
abort and PCI compliant target abort.
PCISTS also indicates the DEVSEL# timing that has been set by the IGD.
B/D/F/Type: 0/2/0/PCI
Address Offset: 6–7h
Reset Value: 0090h
Access: RO, RO-V
Size: 16 bits
BIOS Optimal Default 0h
Bit Access
Reset
Value
RST/
PWR
Description
15 RO 0b Uncore
Detected Parity Error (DPE)
Since the IGD does not detect parity, this bit is always hardwired
to 0.
14 RO 0b Uncore
Signaled System Error (SSE)
The IGD never asserts SERR#; therefore, this bit is hardwired to
0.
13 RO 0b Uncore
Received Master Abort Status (RMAS)
The IGD never gets a Master Abort; therefore, this bit is
hardwired to 0.
12 RO 0b Uncore
Received Target Abort Status (RTAS)
The IGD never gets a Target Abort; therefore, this bit is
hardwired to 0.
11 RO 0b Uncore
Signaled Target Abort Status (STAS)
Hardwired to 0. The IGD does not use target abort semantics.
10:9 RO 00b Uncore
DEVSEL Timing (DEVT)
N/A. These bits are hardwired to "00".
8RO 0bUncore
Master Data Parity Error Detected (DPD)
Since Parity Error Response is hardwired to disabled (and the IGD
does not do any parity detection), this bit is hardwired to 0.
7RO 1bUncore
Fast Back-to-Back (FB2B)
Hardwired to 1. The IGD accepts fast back-to-back when the
transactions are not to the same agent.
6RO 0bUncore
User Defined Format (UDF)
Hardwired to 0.
5RO 0bUncore
66 MHz PCI Capable (C66)
N/A – Hardwired to 0.
4RO 1bUncore
Capability List (CLIST)
This bit is set to 1 to indicate that the register at 34h provides an
offset into the function's PCI Configuration Space containing a
pointer to the location of the first item in the list.
3RO-V 0b Uncore
Interrupt Status (INTSTS)
This bit reflects the state of the interrupt in the device. Only
when the Interrupt Disable bit in the command register is a 0 and
this Interrupt Status bit is a 1, will the devices INTx# signal be
asserted.
2:0 RO 0h Reserved (RSVD)