Datasheet

Processor Configuration Registers
128 Datasheet, Volume 2
2.6.47 DCTL2—Device Control 2 Register
B/D/F/Type: 0/1/0–2/PCI
Address Offset: C8–C9h
Reset Value: 0000h
Access: RW-V, RW
Size: 16 bits
BIOS Optimal Default 0000h
Bit Access
Reset
Value
RST/
PWR
Description
15:12 RO 0h Reserved (RSVD)
11 RW-V 0b Uncore
Latency Tolerance and BW Reporting Mechanism Enable
(LTREN)
When set to 1b, this bit enables the Latency Tolerance &
Bandwidth Requirement Reporting (LTBWR) mechanism.
This bit is required for all Functions that support the LTBWR
Capability. For a Multi-Function device associated with an
upstream port of a device that implements LTBWR, the bit in
Function 0 is of type RW, and only Function 0 controls the
component’s Link behavior. In all other Functions of that device,
this bit is of type RsvdP.
Components that do not implement LTBWR are permitted to
hardwire this bit to 0b.
Reset Value of this bit is 0b.
This bit is cleared when the port goes to DL_down state.
Hardware ignores the value of this bit.
10:6 RO 0h Reserved (RSVD)
5RW 0bUncore
ARI Forward Enable (ARIFEN)
When set, the Downstream Port disables its traditional Device
Number field being 0 enforcement when turning a Type 1
Configuration Request into a Type 0 Configuration Request,
permitting access to Extended Functions in an ARI Device
immediately below the Port.
Reset Value of this bit is 0b. It must be hardwired to 0b if the ARI
Forwarding Supported bit is 0b.
4:0 RO 0h Reserved (RSVD)