Datasheet

Datasheet, Volume 2 105
Processor Configuration Registers
2.6.26 PM_CS—Power Management Control/Status Register
24:22 RO 000b Uncore
Auxiliary Current (AUXC)
Hardwired to 0 to indicate that there are no 3.3Vaux auxiliary
current requirements.
21 RO 0b Uncore
Device Specific Initialization (DSI)
Hardwired to 0 to indicate that special initialization of this device
is NOT required before generic class device driver is to use it.
20 RO 0b Uncore
Auxiliary Power Source (APS)
Hardwired to 0.
19 RO 0b Uncore
PME Clock (PMECLK)
Hardwired to 0 to indicate this device does NOT support PME#
generation.
18:16 RO 011b Uncore
PCI PM CAP Version (PCIPMCV)
A value of 011b indicates that this function complies with
Revision 1.2 of the PCI Power Management Interface
Specification.
(Was previously hardwired to 02h to indicate there are 4 bytes of
power management registers implemented and that this device
complies with revision 1.1 of the PCI Power Management
Interface Specification.)
15:8 RO-V 90h Uncore
Pointer to Next Capability (PNC)
This contains a pointer to the next item in the capabilities list. If
MSICH (CAPL[0] @ 7Fh) is 0, then the next item in the
capabilities list is the Message Signaled Interrupts (MSI)
capability at 90h. If MSICH (CAPL[0] @ 7Fh) is 1, then the next
item in the capabilities list is the PCI Express capability at A0h.
7:0 RO 01h Uncore
Capability ID (CID)
Value of 01h identifies this linked list item (capability structure)
as being for PCI Power Management registers.
B/D/F/Type: 0/1/0–2/PCI
Address Offset: 84–87h
Reset Value: 00000008h
Access: RO, RW
Size: 32 bits
BIOS Optimal Default 000000h
Bit Access
Reset
Value
RST/
PWR
Description
31:16 RO 0h Reserved (RSVD)
15 RO 0b Uncore
PME Status (PMESTS)
This bit indicates that this device does not support PME#
generation from D3cold.
14:13 RO 00b Uncore
Data Scale (DSCALE)
This field indicates that this device does not support the power
management data register.
12:9 RO 0h Uncore
Data Select (DSEL)
This field indicates that this device does not support the power
management data register.
B/D/F/Type: 0/1/0–2/PCI
Address Offset: 80–83h
Reset Value: C8039001h
Access: RO, RO-V
Size: 32 bits
Bit Access
Reset
Value
RST/
PWR
Description