Datasheet

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Datasheet, Volume 2 103

Processor Configuration Registers

2.6.24 BCTRL—Bridge Control Register

This register provides extensions to the PCICMD register that are specific to PCI-PCI

bridges. The BCTRL provides additional control for the secondary interface (that is, PCI

Express-G) as well as some bits that affect the overall behavior of the "virtual" Host-

PCI Express bridge embedded within the processor; such as VGA compatible address

ranges mapping.

B/D/F/Type: 0/1/0–2/PCI

Address Offset: 3E–3Fh

Reset Value: 0000h

Access: RO, RW

Size: 16 bits

BIOS Optimal Default 0h

Bit Access

Reset

Value

RST/

PWR

Description

15:12 RO 0h Reserved (RSVD)

11 RO 0b Uncore

Discard Timer SERR# Enable (DTSERRE)

Not Applicable or Implemented. Hardwired to 0.

10 RO 0b Uncore

Discard Timer Status (DTSTS)

Not Applicable or Implemented. Hardwired to 0.

9RO 0bUncore

Secondary Discard Timer (SDT)

Not Applicable or Implemented. Hardwired to 0.

8RO 0bUncore

Primary Discard Timer (PDT)

Not Applicable or Implemented. Hardwired to 0.

7RO 0bUncore

Fast Back-to-Back Enable (FB2BEN)

Not Applicable or Implemented. Hardwired to 0.

6RW 0bUncore

Secondary Bus Reset (SRESET)

Setting this bit triggers a hot reset on the corresponding PCI

Express Port. This will force the LTSSM to transition to the Hot

Reset state (using Recovery) from L0, L0s, or L1 states.

5RO 0bUncore

Master Abort Mode (MAMODE)

Does not apply to PCI Express. Hardwired to 0.

4RW 0bUncore

VGA 16-bit Decode (VGA16D)

Enables the PCI-to-PCI bridge to provide 16-bit decoding of VGA

I/O address precluding the decoding of alias addresses every

1 KB. This bit only has meaning if bit 3 (VGA Enable) of this

register is also set to 1, enabling VGA I/O decoding and

forwarding by the bridge.

0 = Execute 10-bit address decodes on VGA I/O accesses.

1 = Execute 16-bit address decodes on VGA I/O accesses.

3RW 0bUncore

VGA Enable (VGAEN)

This bit controls the routing of processor initiated transactions

targeting VGA compatible I/O and memory address ranges. See

the VGAEN/MDAP table in Device 0, offset 97h[0].