Mobile 3rd Generation Intel® Core™ Processor Family Datasheet – Volume 2 of 2 June 2012 Document Number: 326769-002
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Contents 1 Introduction ............................................................................................................ 13 2 Processor Configuration Registers ........................................................................... 15 2.1 Register Terminology ......................................................................................... 15 2.2 PCI Devices and Functions.................................................................................. 16 2.3 System Address Map ..
2.6 4 2.5.10 CAPPTR—Capabilities Pointer Register ....................................................54 2.5.11 PXPEPBAR—PCI Express* Egress Port Base Address Register .....................54 2.5.12 MCHBAR—Host Memory Mapped Register Range Base Register ..................55 2.5.13 GGC—GMCH Graphics Control Register ...................................................55 2.5.14 DEVEN—Device Enable Register.............................................................57 2.5.
2.7 2.8 2.6.26 PM_CS—Power Management Control/Status Register ............................. 105 2.6.27 SS_CAPID—Subsystem ID and Vendor ID Capabilities Register................ 107 2.6.28 SS—Subsystem ID and Subsystem Vendor ID Register........................... 107 2.6.29 MSI_CAPID—Message Signaled Interrupts Capability ID Register ............. 108 2.6.30 MC—Message Control Register ............................................................ 109 2.6.31 MA—Message Address Register .....................
2.9 2.10 6 2.8.13 SVID2—Subsystem Vendor Identification Register .................................. 156 2.8.14 SID2—Subsystem Identification Register .............................................. 157 2.8.15 ROMADR—Video BIOS ROM Base Address Register ................................. 157 2.8.16 CAPPOINT—Capabilities Pointer Register ............................................... 157 2.8.17 INTRLINE—Interrupt Line Register ....................................................... 158 2.8.
2.11 2.12 2.13 2.10.44 RCTL—Root Control Register ............................................................... 202 2.10.45 LCAP2—Link Capabilities 2 Register ..................................................... 202 PCI Device 6 Extended Configuration Registers.................................................... 203 2.11.1 PVCCAP1—Port VC Capability Register 1 ............................................... 204 2.11.2 PVCCAP2—Port VC Capability Register 2 ..............................................
2.14 2.15 2.16 2.17 2.18 8 2.13.3 SC_IO_LATENCY_C0—IO Latency configuration Register ......................... 242 2.13.4 TC_SRFTP_C0–Self Refresh Timing Parameters Register ......................... 242 2.13.5 PM_PDWN_config_C0–Power-down Configuration Register ...................... 243 2.13.6 TC_RFP_C0—Refresh Parameters Register............................................. 244 2.13.7 TC_RFTP_C0—Refresh Timing Parameters Register.................................
2.19 2.20 2.21 2.18.30 FRCDL_REG—Fault Recording Low Register........................................... 293 2.18.31 FRCDH_REG—Fault Recording High Register ......................................... 294 2.18.32 VTPOLICY—DMA Remap Engine Policy Control Register........................... 295 PCU MCHBAR Registers .................................................................................... 296 2.19.1 MEM_TRML_ESTIMATION_CONFIG—Memory Thermal Estimation Configuration Register..........................
Figures 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 System Address Range Example ..........................................................................19 DOS Legacy Address Range ................................................................................20 Main Memory Address Range...............................................................................22 PCI Memory Address Range ................................................................................
Revision History Revision Number 001 002 Description Initial release • • Revision Date April 2012 Updated Section 2.6 to reflect support for Functions 0–2. Updated Section 2.7 to relfect support for Functions 0–2.
Datasheet, Volume 2
Introduction 1 Introduction This is Volume 2 of the Datasheet for the following products: • Mobile 3rd Generation Intel® Core™ processor family The processor contains one or more PCI devices within a single physical component. The configuration registers for these devices are mapped as devices residing on the PCI Bus assigned for the processor socket. This document describes the configuration space registers or device-specific control and status registers (CSRs) only.
Introduction 14 Datasheet, Volume 2
Processor Configuration Registers 2 Processor Configuration Registers This chapter contains the following: • Register terminology • PCI Devices and Functions on processor • System address map • Processor register introduction • Detailed register bit descriptions 2.1 Register Terminology Table 2-1 lists the register-related terminology and access attributes that are used in this document. Table 2-2 provides the attribute modifiers. Table 2-1.
Processor Configuration Registers Table 2-2. Register Attribute Modifiers Attribute Modifier Applicable Attribute RO (w/ -V) RW S RW1C Description Sticky: These bits are only re-initialized to their Reset Value by a "Power Good Reset". Note: Does not apply to RO (constant) bits. RW1S -K RW RW -L WO Key: These bits control the ability to write other bits (identified with a 'Lock' modifier) Lock: Hardware can make these bits "Read Only" using a separate configuration bit or other logic.
Processor Configuration Registers 2.3 System Address Map The processor supports 512 GB (39 bit) of addressable memory space and 64 KB+3 of addressable I/O space. This section focuses on how the memory space is partitioned and the use of the separate memory regions. I/O address space has simpler mapping and is explained near the end of this section. The processor supports PEG port upper prefetchable base/limit registers. This allows the PEG unit to claim I/O accesses above 32 bit.
Processor Configuration Registers • Device 6, Function 0: (PCIe x4 Controller) — MBASE/MLIMIT – PCI Express port non-prefetchable memory access window. — PMBASE/PMLIMIT – PCI Express port prefetchable memory access window. — PMUBASE/PMULIMIT – PCI Express port upper prefetchable memory access window — IOBASE/IOLIMIT – PCI Express port I/O access window. • Device 2, Function 0: (Integrated Graphics Device (IGD)) — IOBAR – I/O access window for internal graphics.
Processor Configuration Registers Figure 2-1. System Address Range Example Physical Memory (DRAM Controller View) Host/System View 512 GB PCI Memory Add.
Processor Configuration Registers Figure 2-2. DOS Legacy Address Range 000F_FFFFh 000F_0000h System BIOS (Upper) 64 KB 000E_FFFFh 000E_0000h Extended System BIOS (Lower) 64 KB (16KBx4) 000D_FFFFh 1 MB 960 KB 896 KB Expansion Area 128 KB (16KBx8) 000C_0000h 000B_FFFFh 000A_0000h 768 KB Legacy Video Area (SMM Memory) 128 KB 640 KB 0009_FFFFh DOS Area 0000_0000h 2.3.1.
Processor Configuration Registers Compatible SMRAM Address Range (A_0000h–B_FFFFh) When compatible SMM space is enabled, SMM-mode processor accesses to this range route to physical system DRAM at 000A_0000h–000B_FFFFh. PCI Express and DMI originated cycles to enable SMM space are not allowed and are considered to be to the Video Buffer Area, if IGD is not enabled as the VGA device. DMI initiated writes cycles are attempted as peer writes cycles to a VGA enabled PCIe port.
Processor Configuration Registers 2.3.2 Main Memory Address Range (1 MB – TOLUD) This address range extends from 1 MB to the top of Low Usable physical memory that is permitted to be accessible by the processor (as programmed in the TOLUD register). The processor will route all addresses within this range to the DRAM unless it falls into the optional TSEG, optional ISA Hole, or optional IGD stolen VGA memory. Figure 2-3.
Processor Configuration Registers 2.3.2.2 TSEG For processor initiated transactions, the processor relies on correct programming of SMM Range Registers (SMRR) to enforce TSEG protection. TSEG is below IGD stolen memory, which is at the Top of Low Usable physical memory (TOLUD). BIOS will calculate and program the TSEG BASE in Device 0 (TSEGMB), used to protect this region from DMA access.
Processor Configuration Registers 2.3.2.4 DRAM Protected Range (DPR) This protection range only applies to DMA accesses and GMADR translations. It serves a purpose of providing a memory range that is only accessible to processor streams. The DPR range works independent of any other range, including the PMRC checks in VTd. It occurs post any VTd translation.
Processor Configuration Registers 2.3.2.7 Intel® Management Engine (Intel® ME) UMA Intel ME (the AMT Intel Management Engine) can be allocated UMA memory. Intel MEmemory is “stolen” from the top of the Host address map. The Intel ME stolen memory base is calculated by subtracting the amount of memory stolen by the Intel Management Engine from TOM. Only Intel ME can access this space; it is not accessible by or coherent with any processor side accesses. 2.3.
Processor Configuration Registers Figure 2-4.
Processor Configuration Registers Memory requests to this range would then be forwarded to the PCI Express port. This mode is intended for the entry Workstation/Server SKU of the MCH, and would be disabled in typical Desktop systems. When disabled, any access within entire APIC Configuration space (FEC0_0000h to FECF_FFFFh) is forwarded to DMI. 2.3.3.2 HSEG (FEDA_0000h – FEDB_FFFFh) This decode range is not supported on the processor platform. 2.3.3.
Processor Configuration Registers Top of Upper Usable DRAM (TOUUD) The Top of Upper Usable Dram (TOUUD) register reflects the total amount of addressable DRAM. If remap is disabled, TOUUD will reflect TOM minus Intel Management Engine stolen size. If remap is enabled, then it will reflect the remap limit.
Processor Configuration Registers 2.3.4.
Processor Configuration Registers 2.3.4.5 Programming Model The memory boundaries of interest are: • Bottom of Logical Address Remap Window defined by the REMAPBASE register, which is calculated and loaded by BIOS. • Top of Logical Address Remap Window defined by the REMAPLIMIT register, which is calculated and loaded by BIOS. • Bottom of Physical Remap Memory defined by the existing TOLUD register.
Processor Configuration Registers 2.3.4.5.1 Case 1 – Less than 4 GB of Physical Memory (no remap) Figure 2-5.
Processor Configuration Registers 2.3.4.5.2 Case 2 – Greater than 4 GB of Physical Memory Figure 2-6. Case 2 – Greater than 4 GB of Physical Memory Physical Memory (DRAM Controller View) Host/System View 512 GB High PCI Memory Add.
Processor Configuration Registers Example: 5 GB of Physical Memory, with 1 GB allocated to Memory Mapped IO • Populated Physical Memory = 5 GB • Address Space allocated to memory mapped IO (including Flash, APIC, and Intel TXT) = 1 GB • Remapped Physical Memory = 1 GB • TOM – 01_4000_0000h (5 GB) • ME stolen size – 00000b (0 MB) • TOUUD – 01_8000_0000h (6 GB) (1 MB aligned) • TOLUD – 00_C000_000h (3 GB) • REMAPBASE – 01_4000_0000h (5 GB) • REMAPLIMIT – 01_7FF0_0000h (6 GB–1) The Remap window is inclusive o
Processor Configuration Registers MSI Interrupts At fixed address below 4 GB GMADR 64 bit BARs GTTMMADR 64 bit BARs MBASE/MLIMIT PXPEPBAR 39 bit BAR DMIBAR 39 bit BAR MCHBAR 39 bit BAR TMBAR 64 bit BAR PMBASE/PMLIMIT 64 bit BAR (using Upper PMBASE/PMLIMIT) CHAPADR 64 bit BAR GFXVTBAR 39 bit BARs VTDPVC0BAR 39 bit BARs Implementation Notes • Remap applies to transactions from all interfaces. All upstream PEG/DMI transactions that are snooped get remapped.
Processor Configuration Registers 2.3.5 PCI Express* Configuration Address Space PCIEXBAR is located in Device 0 configuration space. The processor detects memory accesses targeting PCIEXBAR. BIOS must assign this address range such that it will not conflict with any other address ranges. See the configuration portion of this document for more details. 2.3.6 PCI Express* Graphics Attach (PEG) The processor can be programmed to direct memory accesses to a PCI Express interface.
Processor Configuration Registers 2.3.7 Graphics Memory Address Ranges The integrated memory controller can be programmed to direct memory accesses to IGD when addresses are within any of two ranges specified using registers in MCH Device 2 configuration space. 1. The Graphics Memory Aperture Base Register (GMADR) is used to access graphics memory allocated using the graphics translation table. 2.
Processor Configuration Registers 2.3.8 System Management Mode (SMM) The Core handles all SMM mode transaction routing. Also, the platform no longer supports HSEG. The processor will not allow I/O devices access to CSEG/TSEG/HSEG ranges. DMI Interface and PCI Express masters are not allowed to access the SMM space. Table 2-4. 2.3.
Processor Configuration Registers 2.3.11 I/O Address Space The system agent generates either DMI Interface or PCI Express bus cycles for all processor I/O accesses that it does not claim. Configuration Address Register (CONFIG_ADDRESS) and the Configuration Data Register (CONFIG_DATA) are used to generate PCI configuration space access. The processor allows 64K+3 bytes to be addressed within the I/O space.
Processor Configuration Registers The processor also forwards accesses to the Legacy VGA I/O ranges according to the settings in the PEG configuration registers BCTRL (VGA Enable) and PCICMD (IOAE), unless a second adapter (monochrome) is present on the DMI Interface/PCI (or ISA). The presence of a second graphics adapter is determined by the MDAP configuration bit. When MDAP is set, the processor will decode legacy monochrome I/O ranges and forward them to the DMI Interface.
Processor Configuration Registers DMI Interface Accesses to the processor that Cross Device Boundaries The processor does not support transactions that cross device boundaries. This should never occur because PCI Express transactions are not allowed to cross a 4 KB boundary. For reads, the processor will provide separate completion status for each naturally-aligned 64 byte block or, if chaining is enabled, each 128 byte block.
Processor Configuration Registers e. Internal Graphics GMADR writes and GMADR reads are not supported. 4. VCm accesses a. See DMI2 specification for TC mapping to VCm. VCm access only map to Intel ME stolen DRAM. These transactions carry the direct physical DRAM address (no redirection or remapping of any kind will occur). This is how the PCH Intel Management Engine accesses its dedicated DRAM stolen space. b.
Processor Configuration Registers 2.3.13.2 PCI Express* Interface Decode Rules All “SNOOP semantic” PCI Express transactions are kept coherent with processor caches. All “Snoop not required semantic” cycles must reference the direct DRAM address range. PCI Express non-snoop initiated cycles are not snooped.
Processor Configuration Registers Figure 2-8. PEG Upstream VC0 Memory Map Upstream Initiated VC0 Cycle Memory Map 2 TB TOM = total physical DRAM 64 GB REMAPLIMIT TOUUD REMAPBASE 4 GB FEE0_0000h – FEEF_FFFFh( MSI) GMADR TOLUD TSEG_BASE TOLUD – (Gfx Stolen) – (Gfx GTT stolen) (TSEG) TSEG_BASE – DPR A0000h–BFFFFh (VGA) mem writes peer write (if matching PEG range else invalid) mem reads Invalid transaction mem writes Route based on SNR bit. mem reads Route based on SNR bit.
Processor Configuration Registers Accesses to the VGA memory range are directed to IGD depend on the configuration. The configuration is specified by: • Internal Graphics Controller in Device 2 is enabled (DEVEN.D2EN bit 4) • Internal Graphics VGA in Device 0 Function 0 is enabled through register GGC bit 1. • IGD Memory accesses (PCICMD2 04 – 05h, MAE bit 1) in Device 2 configuration space are enabled.
Processor Configuration Registers For regions mapped outside of the IGD (or if IGD is disabled), the legacy VGA memory range A0000h–BFFFFh are mapped either to the DMI Interface or PCI Express depending on the programming of the VGA Enable bit in the BCTRL configuration register in the PEG configuration space, and the MDAPxx bits in the Legacy Access Control (LAC) register in Device 0 configuration space. The same register controls mapping VGA I/O address ranges.
Processor Configuration Registers MDA Present (MDAP): This bit works with the VGA Enable bit in the BCTRL register of Device 1 to control the routing of processor initiated transactions targeting MDA compatible I/O and memory address ranges. This bit should not be set when the VGA Enable bit is not set. If the VGA enable bit is set, accesses to I/O address range x3BCh– x3BFh are forwarded to DMI Interface.
Processor Configuration Registers 2.5 PCI Device 0 Function 0 Configuration Space Registers Table 2-8.
Processor Configuration Registers Table 2-8. 2.5.
Processor Configuration Registers 2.5.2 DID—Device Identification Register This register combined with the Vendor Identification register uniquely identifies any PCI device. B/D/F/Type: Address Offset: Reset Value: Access: Size: 2.5.3 0/0/0/PCI 2–3h 0150h RO-FW, RO-V 16 bits Bit Access Reset Value RST/ PWR 15:4 RO-FW 015h Uncore Device Identification Number MSB (DID_MSB) This is the upper part of device identification assigned to the processor.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.5.4 0/0/0/PCI 4–5h 0006h RO, RW 16 bits 00h Bit Access Reset Value RST/ PWR 7 RO 0b Uncore Address/Data Stepping Enable (ADSTEP) Address/data stepping is not implemented in the processor, and this bit is hardwired to 0. Writes to this bit position have no effect.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Reset Value RST/ PWR Description 14 RW1C 0b Uncore Signaled System Error (SSE) This bit is set to 1 when Device 0 generates an SERR message over DMI for any enabled Device 0 error condition. Device 0 error conditions are enabled in the PCICMD, ERRCMD, and DMIUEMSK registers. Device 0 error flags are read/reset from the PCISTS, ERRSTS, or DMIUEST registers.
Processor Configuration Registers 2.5.5 RID—Revision Identification Register This register contains the revision number of Device 0. These bits are read only and writes to this register have no effect. B/D/F/Type: Address Offset: Reset Value: Access: Size: 2.5.
Processor Configuration Registers 2.5.7 HDR—Header Type Register This register identifies the header layout of the configuration space. No physical register exists at this location. B/D/F/Type: Address Offset: Reset Value: Access: Size: 2.5.8 0/0/0/PCI Eh 00h RO 8 bits Bit Access Reset Value RST/ PWR 7:0 RO 00h Uncore Description PCI Header (HDR) This field always returns 0 to indicate that the Host Bridge is a single function device with standard header layout.
Processor Configuration Registers 2.5.10 CAPPTR—Capabilities Pointer Register The CAPPTR provides the offset that is the pointer to the location of the first device capability in the capability list. B/D/F/Type: Address Offset: Reset Value: Access: Size: 2.5.11 0/0/0/PCI 34h E0h RO 8 bits Bit Access Reset Value RST/ PWR 7:0 RO E0h Uncore Description Capabilities Pointer (CAPPTR) Pointer to the offset of the first capability ID register block.
Processor Configuration Registers 2.5.12 MCHBAR—Host Memory Mapped Register Range Base Register This is the base address for the Host Memory Mapped Configuration space. There is no physical memory within this 32 KB window that can be addressed. The 32 KB reserved by this register does not alias to any PCI 2.3 compliant memory mapped space. On reset, the Host MMIO Memory Mapped Configuration space is disabled and must be enabled by writing a 1 to MCHBAREN [Device 0, offset 48h, bit 0].
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 9:8 Access RW-L 0/0/0/PCI 50–51h 0028h RW-L, RW-KL 16 bits 00h Reset Value 0h RST/ PWR Description Uncore GTT Graphics Memory Size (GGMS) This field is used to select the amount of Main Memory that is pre-allocated to support the Internal Graphics Translation Table. The BIOS ensures that memory is pre-allocated only when Internal graphics is enabled.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.5.14 0/0/0/PCI 50–51h 0028h RW-L, RW-KL 16 bits 00h Bit Access Reset Value RST/ PWR 2 RO 0h Reserved (RSVD) Description 1 RW-L 0b Uncore IGD VGA Disable (IVD) 0 = Enable. Device 2 (IGD) claims VGA memory and I/O cycles, the Sub-Class Code within Device 2 Class Code register is 00. 1 = Disable.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Reset Value RST/ PWR Device 4 Enable (D4EN) 0 = Bus 0 Device 4 is disabled and not visible. 1 = Bus 0 Device 4 is enabled and visible. This bit will be set to 0b and remain 0b if Device 4 capability is disabled.
Processor Configuration Registers 2.5.15 PAVPC—Protected Audio Video Path Control Register All the bits in this register are locked by Intel TXT. When locked, the RW bits are RO. B/D/F/Type: Address Offset: Reset Value: Access: Size: 2.5.16 0/0/0/PCI 58–5Bh 00000000h RW-L, RW-KL 32 bits Bit Access Reset Value 31:3 RO 0h Reserved (RSVD) PAVP Lock (PAVPLCK) This bit will lock all writeable contents in this register when set (including itself). Only a hardware reset can unlock the register again.
Processor Configuration Registers 2.5.17 PCIEXBAR—PCI Express* Register Range Base Address Register This is the base address for the PCI Express configuration space. This window of addresses contains the 4 KB of configuration space for each PCI Express device that can potentially be part of the PCI Express Hierarchy associated with the Uncore. There is no actual physical memory within this window of up to 256 MB that can be addressed.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Access Reset Value RST/ PWR Description 27 RW-V 0b Uncore 128 MB Base Address Mask (ADMSK128) This bit is either part of the PCI Express Base Address (RW) or part of the Address Mask (RO, read 0b), depending on the value of bits 2:1 in this register.
Processor Configuration Registers 2.5.18 DMIBAR—Root Complex Register Range Base Address Register This is the base address for the Root Complex configuration space. This window of addresses contains the Root Complex Register set for the PCI Express Hierarchy associated with the Host Bridge. There is no physical memory within this 4 KB window that can be addressed. The 4 KB reserved by this register does not alias to any PCI 2.3 compliant memory mapped space.
Processor Configuration Registers 2.5.19 MESEG_BASE—Intel® Management Engine Base Address Register This register determines the Base Address register of the memory range that is preallocated to the Intel Management Engine. Together with the MESEG_MASK register it controls the amount of memory allocated to the ME. This register must be initialized by the configuration software. For the purpose of address decode, address bits A[19:0] are assumed to be 0.
Processor Configuration Registers 2.5.20 MESEG_MASK—Intel® Management Engine Limit Address Register This register determines the Mask Address register of the memory range that is preallocated to the Intel Management Engine. Together with the MESEG_BASE register it controls the amount of memory allocated to the ME. This register is locked by Intel TXT. Note: BIOS must program MESEG_BASE and MESEG_MASK so that Intel ME stolen Memory is carved out from TOM.
Processor Configuration Registers 2.5.21 PAM0—Programmable Attribute Map 0 Register This register controls the read, write and shadowing attributes of the BIOS range from F_0000h to F_FFFFh. The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 KB to 1 MB address range. Seven Programmable Attribute Map (PAM) registers are used to support these features. Cacheability of these areas is controlled using the MTRR register in the core.
Processor Configuration Registers 2.5.22 PAM1—Programmable Attribute Map 1 Register This register controls the read, write and shadowing attributes of the BIOS range from C_0000h to C_7FFFh. The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 KB to 1 MB address range. Seven Programmable Attribute Map (PAM) registers are used to support these features. Cacheability of these areas is controlled using the MTRR register in the core.
Processor Configuration Registers 2.5.23 PAM2—Programmable Attribute Map 2 Register This register controls the read, write and shadowing attributes of the BIOS range from C_8000h to C_FFFFh. The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 KB to 1 MB address range. Seven Programmable Attribute Map (PAM) registers are used to support these features. Cacheability of these areas is controlled using the MTRR register in the core.
Processor Configuration Registers 2.5.24 PAM3—Programmable Attribute Map 3 Register This register controls the read, write and shadowing attributes of the BIOS range from D0000h to D7FFFh. The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 KB to 1 MB address range. Seven Programmable Attribute Map (PAM) registers are used to support these features. Cacheability of these areas is controlled using the MTRR register in the core.
Processor Configuration Registers 2.5.25 PAM4—Programmable Attribute Map 4 Register This register controls the read, write and shadowing attributes of the BIOS range from D8000h to DFFFFh. The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 KB to 1 MB address range. Seven Programmable Attribute Map (PAM) registers are used to support these features. Cacheability of these areas is controlled using the MTRR register in the core.
Processor Configuration Registers 2.5.26 PAM5—Programmable Attribute Map 5 Register This register controls the read, write and shadowing attributes of the BIOS range from E_0000h to E_7FFFh. The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 KB to 1 MB address range. Seven Programmable Attribute Map (PAM) registers are used to support these features. Cacheability of these areas is controlled using the MTRR register in the core.
Processor Configuration Registers 2.5.27 PAM6—Programmable Attribute Map 6 Register This register controls the read, write and shadowing attributes of the BIOS range from E_8000h to E_FFFFh. The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 KB to 1 MB address range. Seven Programmable Attribute Map (PAM) registers are used to support these features. Cacheability of these areas is controlled using the MTRR register in the core.
Processor Configuration Registers 2.5.28 LAC—Legacy Access Control Register This 8-bit register controls steering of MDA cycles and a fixed DRAM hole from 15– 16 MB. There can only be at most one MDA device in the system. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Reset Value RST/ PWR Description Uncore Hole Enable (HEN) This field enables a memory hole in DRAM space. The DRAM that lies "behind" this space is not remapped. 0 = No memory hole.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 2 Datasheet, Volume 2 Access RW 0/0/0/PCI 87h 00h RW 8 bits 0h Reset Value 0b RST/ PWR Description Uncore PEG12 MDA Present (MDAP12) This bit works with the VGA Enable bits in the BCTRL register of Device 1 Function 2 to control the routing of processor initiated transactions targeting MDA compatible I/O and memory address ranges.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 1 74 Access RW 0/0/0/PCI 87h 00h RW 8 bits 0h Reset Value 0b RST/ PWR Description Uncore PEG11 MDA Present (MDAP11) This bit works with the VGA Enable bits in the BCTRL register of Device 1 Function 1 to control the routing of processor initiated transactions targeting MDA compatible I/O and memory address ranges.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 0 Datasheet, Volume 2 Access RW 0/0/0/PCI 87h 00h RW 8 bits 0h Reset Value 0b RST/ PWR Description Uncore PEG10 MDA Present (MDAP10) This bit works with the VGA Enable bits in the BCTRL register of Device 1 Function 0 to control the routing of processor initiated transactions targeting MDA compatible I/O and memory address ranges.
Processor Configuration Registers 2.5.29 REMAPBASE—Remap Base Address Register B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 76 0/0/0/PCI 90–97h 0000000FFFF00000h RW-L, RW-KL 64 bits 000000000000h Bit Access Reset Value 63:36 RO 0h 35:20 RW-L FFFFh 19:1 RO 0h 0 RW-KL 0b RST/ PWR Description Reserved (RSVD) Uncore Remap Base Address (REMAPBASE) The value in this register defines the lower boundary of the Remap window.
Processor Configuration Registers 2.5.30 REMAPLIMIT—Remap Limit Address Register B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.5.31 0/0/0/PCI 98–9Fh 0000000000000000h RW-L, RW-KL 64 bits 000000000000h Bit Access Reset Value 63:36 RO 0h 35:20 RW-L 0000h 19:1 RO 0h 0 RW-KL 0b RST/ PWR Description Reserved (RSVD) Uncore Remap Lim Remap Base register, the Remap window is disabled. These Bits are Intel TXT lockable.
Processor Configuration Registers 2.5.32 TOUUD—Top of Upper Usable DRAM Register This 64 bit register defines the Top of Upper Usable DRAM. Configuration software must set this value to TOM minus all Intel ME stolen memory if reclaim is disabled. If reclaim is enabled, this value must be set to reclaim limit + 1 byte, 1 MB aligned, since reclaim limit is 1 MB aligned. Address bits 19:0 are assumed to be 000_0000h for the purposes of address comparison.
Processor Configuration Registers 2.5.33 BDSM—Base Data of Stolen Memory Register This register contains the base address of graphics data stolen DRAM memory. BIOS determines the base of graphics data stolen memory by subtracting the graphics data stolen memory size (PCI Device 0 offset 52 bits 7:4) from TOLUD (PCI Device 0 offset BCh bits 31:20). B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 2.5.
Processor Configuration Registers 2.5.35 TSEGMB—TSEG Memory Base Register This register contains the base address of TSEG DRAM memory. BIOS determines the base of TSEG memory which must be at or below Graphics Base of GTT Stolen Memory (PCI Device 0 Offset B4h bits 31:20). Note: BIOS must program TSEGMB to an 8 MB naturally aligned boundary. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 2.5.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 2.5.37 Access 0/0/0/PCI BC–BFh 00100000h RW-KL, RW-L 32 bits 00000h Reset Value 31:20 RW-L 001h 19:1 RO 0h 0 RW-KL 0b RST/ PWR Description Uncore Top of Low Usable DRAM (TOLUD) This register contains bits 31:20 of an address one byte above the maximum DRAM memory below 4 GB that is usable by the operating system.
Processor Configuration Registers 2.5.38 CAPID0_A—Capabilities A Register This register control of bits in this register are only required for customer visible SKU differentiation.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default: Bit 2 Datasheet, Volume 2 Access RO-FW 0/0/0/PCI E4–E7h 00000000h RO-FW, RO-KFW 32 bits 000000h Reset Value 0b RST/ PWR Description Uncore IA Overclocking Enabled by DSKU (OC_ENABLED_DSKU) The default constant (non-fuse) value is zero. When the VDM sets this bit, OC will be applied if OC_CTL_SSKU points to DSKU.
Processor Configuration Registers 2.5.39 CAPID0_B—Capabilities B Register Control of bits in this register are only required for customer visible SKU differentiation. B/D/F/Type: Address Offset: Default Value: Access: Size: BIOS Optimal Default: RST/ PWR Bit Access Reset Value 31 RO-FW 0h Reserved (RSVD) 30 RO-FW 0b Reserved (RSVD) 29 RO-FW 0b Reserved (RSVD) 28 RO-FW 0b Uncore SMT Capability (SMT) This setting indicates whether or not the processor is SMT capable.
Processor Configuration Registers B/D/F/Type: Address Offset: Default Value: Access: Size: BIOS Optimal Default: 0/0/0/PCI E8-EBh 00100000h RO-FW, RO-KFW 32 bits 000000h RST/ PWR Description Bit Access Reset Value 11 RO-FW 0b Reserved (RSVD) 10:8 RO-FW 000b Reserved (RSVD) 7 RO-FW 0b Reserved (RSVD) Datasheet, Volume 2 Uncore DDR3 Maximum Frequency Capability (DMFC) PCODE will update this field with the value of FUSE_DMFC, and then apply SSKU overrides.
Processor Configuration Registers 2.6 PCI Device 1 Function 0–2 Configuration Space Registers Table 2-9.
Processor Configuration Registers Table 2-9. 2.6.
Processor Configuration Registers 2.6.2 DID—Device Identification Register This register combined with the Vendor Identification register uniquely identifies any PCI device. B/D/F/Type: Address Offset: Reset Value: Access: Size: 2.6.3 0/1/0–2/PCI 2–3h 0151h RO-FW 16 bits Bit Access Reset Value RST/ PWR Description 15:0 RO-FW 0151h Uncore Device Identification Number MSB (DID_MSB) Identifier assigned to the processor root port (virtual PCI-to-PCI bridge, PCI Express Graphics port).
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Reset Value RST/ PWR Description Uncore SERR# Message Enable (SERRE) This bit controls the root port's SERR# messaging. The processor communicates the SERR# condition by sending an SERR message to the PCH. This bit, when set, enables reporting of non-fatal and fatal errors detected by the device to the Root Complex.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 2.6.4 Access 0/1/0–2/PCI 4–5h 0000h RO, RW 16 bits 00h Reset Value RST/ PWR Description 1 RW 0b Uncore Memory Access Enable (MAE) 0 = All of device's memory space is disabled. 1 = Enable the Memory and Pre-fetchable memory address ranges defined in the MBASE, MLIMIT, PMBASE, and PMLIMIT registers. 0 RW 0b Uncore IO Access Enable (IOAE) 0 = All of device’s I/O space is disabled.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 12 11 10:9 Access RO RO RO 0/1/0–2/PCI 6–7h 0010h RO, RW1C, RO-V 16 bits 0h Reset Value 0b 0b 00b RST/ PWR Description Uncore Received Target Abort Status (RTAS) This bit is set when a Requester receives a Completion with Completer Abort Completion Status. On a Function with a Type 1 Configuration header, the bit is set when the Completer Abort is received by its Primary Side.
Processor Configuration Registers 2.6.5 RID—Revision Identification Register This register contains the revision number of the processor root port. These bits are read only and writes to this register have no effect. B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 7:0 2.6.
Processor Configuration Registers 2.6.8 HDR—Header Type Register This register identifies the header layout of the configuration space. No physical register exists at this location. B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 7:0 2.6.9 Access RO 0/1/0–2/PCI Eh 81h RO 8 bits Reset Value 81h RST/ PWR Uncore Description Header Type Register (HDR) Device 1 returns 81h to indicate that this is a multi function device with bridge header layout.
Processor Configuration Registers 2.6.11 SUBUSN—Subordinate Bus Number Register This register identifies the subordinate bus (if any) that resides at the level below PCI Express-G. This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI Express-G.
Processor Configuration Registers 2.6.12 IOBASE—I/O Base Address Register This register controls the processor to PCI Express-G I/O access routing based on the following formula: IO_BASE ≤ address ≤ IO_LIMIT Only upper 4 bits are programmable. For the purpose of address decode address bits A[11:0] are treated as 0. Thus, the bottom of the defined I/O address range will be aligned to a 4 KB boundary. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.6.
Processor Configuration Registers 2.6.14 SSTS—Secondary Status Register SSTS is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (that is, PCI Express-G side) of the "virtual" PCI-PCI bridge embedded within the processor.
Processor Configuration Registers 2.6.15 MBASE—Memory Base Address Register This register controls the processor to PCI Express-G non-prefetchable memory access routing based on the following formula: MEMORY_BASE ≤ address ≤ MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are readonly and return zeroes when read. This register must be initialized by the configuration software.
Processor Configuration Registers 2.6.16 MLIMIT—Memory Limit Address Register This register controls the processor to PCI Express-G non-prefetchable memory access routing based on the following formula: MEMORY_BASE ≤ address ≤ MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are read-only and return zeroes when read. This register must be initialized by the configuration software.
Processor Configuration Registers 2.6.17 PMBASE—Prefetchable Memory Base Address Register This register in conjunction with the corresponding Upper Base Address register controls the processor to PCI Express-G prefetchable memory access routing based on the following formula: PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read/write and correspond to address bits A[31:20] of the 40-bit address.
Processor Configuration Registers 2.6.18 PMLIMIT—Prefetchable Memory Limit Address Register This register, in conjunction with the corresponding Upper Limit Address register, controls the processor to PCI Express-G prefetchable memory access routing based on the following formula: PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read/write and correspond to address bits A[31:20] of the 40-bit address.
Processor Configuration Registers 2.6.20 PMLIMITU—Prefetchable Memory Limit Address Upper Register The functionality associated with this register is present in the PEG design implementation.
Processor Configuration Registers 2.6.22 INTRLINE—Interrupt Line Register This register contains interrupt line routing information. The device itself does not use this value; rather, it is used by device drivers and operating systems to determine priority and vector information. B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 7:0 2.6.
Processor Configuration Registers 2.6.24 BCTRL—Bridge Control Register This register provides extensions to the PCICMD register that are specific to PCI-PCI bridges. The BCTRL provides additional control for the secondary interface (that is, PCI Express-G) as well as some bits that affect the overall behavior of the "virtual" HostPCI Express bridge embedded within the processor; such as VGA compatible address ranges mapping.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 2 1 0 2.6.25 Access RW RW RW 0/1/0–2/PCI 3E–3Fh 0000h RO, RW 16 bits 0h Reset Value 0b 0b 0b Description Uncore ISA Enable (ISAEN) Needed to exclude legacy resource decode to route ISA resources to legacy decode path. Modifies the response by the root port to an I/O access issued by the processor that target ISA I/O addresses.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit Access Reset Value RST/ PWR 24:22 RO 000b Uncore Auxiliary Current (AUXC) Hardwired to 0 to indicate that there are no 3.3Vaux auxiliary current requirements. 21 RO 0b Uncore Device Specific Initialization (DSI) Hardwired to 0 to indicate that special initialization of this device is NOT required before generic class device driver is to use it.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Reset Value RST/ PWR PME Enable (PMEE) This bit indicates that this device does not generate PME# assertion from any D-state. 0 = PME# generation not possible from any D State 1 = PME# generation enabled from any D State The setting of this bit has no effect on hardware.
Processor Configuration Registers 2.6.27 SS_CAPID—Subsystem ID and Vendor ID Capabilities Register This capability is used to uniquely identify the subsystem where the PCI device resides. Because this device is an integrated part of the system and not an add-in device, it is anticipated that this capability will never be used. However, it is necessary because Microsoft will test for its presence. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.6.
Processor Configuration Registers 2.6.29 MSI_CAPID—Message Signaled Interrupts Capability ID Register When a device supports MSI it can generate an interrupt request to the processor by writing a predefined data item (a message) to a predefined memory address. The reporting of the existence of this capability can be disabled by setting MSICH (CAPL[0] @ 7Fh). In that case walking this linked list will skip this capability and instead go directly from the PCI PM capability to the PCI Express capability.
Processor Configuration Registers 2.6.30 MC—Message Control Register System software can modify bits in this register, but the device is prohibited from doing so. If the device writes the same message multiple times, only one of those messages is ensured to be serviced. If all of them must be serviced, the device must not generate the same message again until the driver services the earlier one.
Processor Configuration Registers 2.6.31 MA—Message Address Register B/D/F/Type: Address Offset: Reset Value: Access: Size: 2.6.32 0/1/0–2/PCI 94–97h 00000000h RW, RO 32 bits Bit Access Reset Value RST/ PWR 31:2 RW 00000000h Uncore Message Address (MA) Used by system software to assign an MSI address to the device. The device handles an MSI by writing the padded contents of the MD register to this address.
Processor Configuration Registers 2.6.34 PEG_CAP—PCI Express-G Capabilities Register This register indicates PCI Express* device capabilities. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.6.35 0/1/0–2/PCI A2–A3h 0142h RO, RW-O 16 bits 0h Bit Access Reset Value 15:14 RO 0h 13:9 RO 00h RST/ PWR Description Reserved (RSVD) Uncore Interrupt Message Number (IMN) Not Applicable or Implemented. Hardwired to 0.
Processor Configuration Registers 2.6.36 DCTL—Device Control Register This register provides control for PCI Express* device specific capabilities. The error reporting enable bits are in reference to errors detected by this device, not error messages received across the link. The reporting of error messages (ERR_CORR, ERR_NONFATAL, ERR_FATAL) received by Root Port is controlled exclusively by Root Port Command Register.
Processor Configuration Registers 2.6.37 DSTS—Device Status Register This register reflects status corresponding to controls in the Device Control register. The error reporting bits are in reference to errors detected by this device, not errors messages received across the link.
Processor Configuration Registers 2.6.38 LCAP—Link Capabilities Register B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit Reset Value RST/ PWR Description Uncore Port Number (PN) This field indicates the PCI Express port number for the given PCI Express link. Matches the value in Element Self Description[31:24].
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit Access 0/1/0–2/PCI AC–AFh 0261CD03h RO, RO-V, RW-O, RW-OV 32 bits Reset Value 18 RO 0b 17:15 RO 0h RST/ PWR Description Uncore Clock Power Management (CPM) A value of 1b in this bit indicates that the component tolerates the removal of any reference clock(s) when the link is in the L1 and L2/3 Ready link states.
Processor Configuration Registers 2.6.39 LCTL—Link Control Register This register allows control of PCI Express* link. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Access Reset Value 15:12 RO 0h Reserved (RSVD) 0b Uncore Link Autonomous Bandwidth Interrupt Enable (LABIE) When set, this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 6 5 Datasheet, Volume 2 Access RW RW-V 0/1/0–2/PCI B0–B1h 0000h RW, RO, RW-V 16 bits 00h Reset Value 0b 0b 4 RO 0h 3 RO 0b 2 RO 0h 1:0 RW 00b RST/ PWR Description Uncore Common Clock Configuration (CCC) 0 = Indicates that this component and the component at the opposite end of this Link are operating with asynchronous reference clock.
Processor Configuration Registers 2.6.40 LSTS—Link Status Register The register indicates PCI Express* link status.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 0/1/0–2/PCI B2–B3h 1001h RW1C, RO-V, RO 16 bits 0h Bit Access Reset Value 10 RO 0h 9:4 3:0 RO-V RO RST/ PWR Description Reserved (RSVD) 00h Uncore Negotiated Link Width (NLW) This field indicates negotiated link width. This field is valid only when the link is in the L0, L0s, or L1 states (after link width negotiation is successfully completed).
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 16:15 120 Access RW-O 0/1/0–2/PCI B4–B7h 00040000h RW-O, RO 32 bits Reset Value 00b RST/ PWR Description Uncore Slot Power Limit Scale (SPLS) This field specifies the scale used for the Slot Power Limit Value. 00 = 1.0x 01 = 0.1x 10 = 0.01x 11 = 0.001x If this field is written, the link sends a Set_Slot_Power_Limit message.
Processor Configuration Registers 2.6.42 SLOTCTL—Slot Control Register Note: PCI Express* Hot-Plug is not supported on the processor.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 7:6 5 RO RO Reset Value 00b 0b RST/ PWR Description Uncore Reserved for Attention Indicator Control (AIC) If an Attention Indicator is implemented, writes to this field set the Attention Indicator to the written state.
Processor Configuration Registers 2.6.43 SLOTSTS—Slot Status Register This is a PCI Express* Slot related register. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Access Reset Value 15:9 RO 0h Reserved (RSVD) 0b Uncore Reserved for Data Link Layer State Changed (DLLSC) This bit is set when the value reported in the Data Link Layer Link Active field of the Link Status register is changed.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 124 Access 0/1/0–2/PCI BA–BBh 0000h RO, RW1C, RO-V 16 bits 00h Reset Value RST/ PWR Description 3 RW1C 0b Uncore Presence Detect Changed (PDC) A pulse indication that the inband presence detect state has changed. This bit is set when the value reported in Presence Detect State is changed.
Processor Configuration Registers 2.6.44 RCTL—Root Control Register This register allows control of PCI Express* Root Complex specific parameters. The system error control bits in this register determine if corresponding SERRs are generated when our device detects an error (reported in this device's Device Status register) or when an error message is received across the link. Reporting of SERR as controlled by these bits takes precedence over the SERR Enable in the PCI Command Register.
Processor Configuration Registers 2.6.45 RSTS—Root Status Register This register provides information about PCI Express* Root Complex specific parameters. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Access Reset Value 31:18 RO 0h Reserved (RSVD) 0b Uncore PME Pending (PMEP) This bit indicates that another PME is pending when the PME Status bit is set.
Processor Configuration Registers 2.6.46 DCAP2—Device Capabilities 2 Register B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 0/1/0–2/PCI C4–C7h 00000800h RO, RW-O 32 bits 0000000h Bit Access Reset Value 31:12 RO 0h Reserved (RSVD) Latency Tolerance and BW reporting Mechanism Supported (LTRS) A value of 1b indicates support for the optional Latency Tolerance & Bandwidth Requirement Reporting (LTBWR) mechanism capability.
Processor Configuration Registers 2.6.47 DCTL2—Device Control 2 Register B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 128 0/1/0–2/PCI C8–C9h 0000h RW-V, RW 16 bits 0000h Bit Access Reset Value RST/ PWR 15:12 RO 0h Reserved (RSVD) Latency Tolerance and BW Reporting Mechanism Enable (LTREN) When set to 1b, this bit enables the Latency Tolerance & Bandwidth Requirement Reporting (LTBWR) mechanism.
Processor Configuration Registers 2.6.48 LCAP2—Link Capabilities 2 Register B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.6.49 0/1/0–2/MMR CC–CFh 0000000Eh RO-V 32 bits 0000000h Bit Access Reset Value 31:8 RO 0h 7:1 RO-V 07h 0 RO 0h RST/ PWR Description Reserved (RSVD) Uncore Supported Link Speeds Vector (SLSV) This field indicates the supported Link speed(s) of the associated Port.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit Reset Value RST/ PWR Description Powergood Selectable De-emphasis (selectabledeemphasis) When the Link is operating at 5 GT/s speed, selects the level of de-emphasis. Encodings: 1 = -3.5 dB 0 = -6 dB Reset Value is implementation specific, unless a specific value is required for a selected form factor or platform. When the Link is operating at 2.5 GT/s speed, the setting of this bit has no effect.
Processor Configuration Registers 2.6.50 LSTS2—Link Status 2 Register B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Access Reset Value 15:6 RO 0h Reserved (RSVD) 0b Uncore Link Equalization Request (LNKEQREQ) This bit is set by hardware to request the Link equalization process to be performed on the Link. Refer to PCIe Specification, Sections 4.2.3 and 4.2.6.4.2 for details. The Reset Value of this bit is 0b.
Processor Configuration Registers 2.7 PCI Device 1 Function 0–2 Extended Configuration Registers Table 2-10.
Processor Configuration Registers 2.7.1 PVCCAP1—Port VC Capability Register 1 This register describes the configuration of PCI Express* Virtual Channels associated with this port. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.7.
Processor Configuration Registers 2.7.3 PVCCTL—Port VC Control Register B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Access Reset Value 15:4 RO 0h 3:1 0 134 0/1/0–2/MMR 10C–10Dh 0000h RW, RO 16 bits 000h RW RO 000b 0b RST/ PWR Description Reserved (RSVD) Uncore VC Arbitration Select (VCAS) This field will be programmed by software to the only possible value as indicated in the VC Arbitration Capability field.
Processor Configuration Registers 2.7.
Processor Configuration Registers 2.7.5 VC0RCTL—VC0 Resource Control Register This register controls the resources associated with PCI Express* Virtual Channel 0. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 136 0/1/0–2/MMR 114–117h 800000FFh RO, RW 32 bits 000h Bit Access Reset Value RST/ PWR Description 31 RO 1b Uncore VC0 Enable (VC0E) For VC0, this is hardwired to 1 and read only as VC0 can never be disabled.
Processor Configuration Registers 2.7.6 VC0RSTS—VC0 Resource Status Register This register reports the Virtual Channel specific status. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.7.7 0/1/0–2/MMR 11A–11Bh 0002h RO-V 16 bits 0000h Bit Access Reset Value 15:2 RO 0h Reserved (RSVD) VC0 Negotiation Pending (VC0NP) 0 = The VC negotiation is complete. 1 = The VC resource is still in the process of negotiation (initialization or disabling).
Processor Configuration Registers 2.7.
Processor Configuration Registers 2.7.
Processor Configuration Registers 2.7.10 EQCTL4_5—Lane 4/5 Equalization Control Register Lane Equalization Control Register (2 lanes are combined, lane "0" is the lower numbered lane, lane "1" is the higher numbered lane).
Processor Configuration Registers 2.7.11 EQCTL6_7—Lane 6/7 Equalization Control Register Lane Equalization Control Register (2 lanes are combined, lane "0" is the lower numbered lane, lane "1" is the higher numbered lane).
Processor Configuration Registers 2.7.12 EQCTL8_9—Lane 8/9 Equalization Control Register Lane Equalization Control Register (2 lanes are combined, lane "0" is the lower numbered lane, lane "1" is the higher numbered lane).
Processor Configuration Registers 2.7.13 EQCTL10_11—Lane 10/11 Equalization Control Register Lane Equalization Control Register (2 lanes are combined, lane "0" is the lower numbered lane, lane "1" is the higher numbered lane).
Processor Configuration Registers 2.7.14 EQCTL12_13—Lane 12/13 Equalization Control Register Lane Equalization Control Register (2 lanes are combined, lane "0" is the lower numbered lane, lane "1" is the higher numbered lane).
Processor Configuration Registers 2.7.15 EQCTL14_15—Lane 14/15 Equalization Control Register Lane Equalization Control Register (2 lanes are combined, lane "0" is the lower numbered lane, lane "1" is the higher numbered lane).
Processor Configuration Registers 2.7.16 EQCFG—Equalization Configuration Register Lane Equalization Control Register (2 lanes are combined, lane "0" is the lower numbered lane, lane "1" is the higher numbered lane). B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 31:26 RW Reset Value 3Eh RST/ PWR Description Uncore Full Swing Value (FS) FS is used to calculate the transmitter coefficients during Equalization. Default is 62d.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 5:2 Datasheet, Volume 2 Access RW 0/1/0/MMR DD8–DDBh F9404400h RW 32 bits 0h Reset Value 0h 1 RW 0b 0 RO 0h RST/ PWR Uncore Uncore Description Bypass Coefficients During Phase 3 (BYPCOEFPH3) Bit [0]: Controls the value of bit 7 in Symbol 6 of EQ TS1s during "Bypass Phase 3 Adaptation" 1 = use preset 0 = use coefficients The preset is defined by the per-lane DCTP field in EQCTL
Processor Configuration Registers 2.8 PCI Device 2 Configuration Space Registers Table 2-11.
Processor Configuration Registers 2.8.1 VID2—Vendor Identification Register This register combined with the Device Identification register uniquely identifies any PCI device. B/D/F/Type: Address Offset: Reset Value: Access: Size: 2.8.2 0/2/0/PCI 0–1h 8086h RO 16 bits Bit Access Reset Value RST/ PWR 15:0 RO 8086h Uncore Description Vendor Identification Number (VID) PCI standard identification for Intel.
Processor Configuration Registers 2.8.3 PCICMD2—PCI Command Register This 16-bit register provides basic control over the IGD's ability to respond to PCI cycles. The PCICMD Register in the IGD disables the IGD PCI compliant master accesses to main memory.
Processor Configuration Registers 2.8.4 PCISTS2—PCI Status Register PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort and PCI compliant target abort. PCISTS also indicates the DEVSEL# timing that has been set by the IGD.
Processor Configuration Registers 2.8.5 RID2—Revision Identification Register This register contains the revision number for Device 2 Functions 0. These bits are read only and writes to this register have no effect. B/D/F/Type: Address Offset: Reset Value: Access: Size: 2.8.
Processor Configuration Registers 2.8.7 CLS—Cache Line Size Register The IGD does not support this register as a PCI slave. B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 7:0 2.8.8 Access RO 0/2/0/PCI Ch 00h RO 8 bits Reset Value 00h RST/ PWR Description Uncore Cache Line Size (CLS) This field is hardwired to 0s. The IGD as a PCI compliant master does not use the Memory Write and Invalidate command and, in general, does not perform operations based on cache line size.
Processor Configuration Registers 2.8.10 GTTMMADR—Graphics Translation Table, Memory Mapped Range Address Register This register requests allocation for the combined Graphics Translation Table Modification Range and Memory Mapped Range. The range requires 4 MB combined for MMIO and Global GTT aperture, with 2 MB of that used by MMIO and 2 MB used by GTT. GTTADR will begin at (GTTMMADR + 2 MB) while the MMIO base address will be the same as GTTMMADR.
Processor Configuration Registers 2.8.11 GMADR—Graphics Memory Range Address Register GMADR is the PCI aperture used by S/W to access tiled graphics surfaces in a linear fashion. B/D/F/Type: Address Offset: Reset Value: Access: Size: 0/2/0/PCI 18–1Fh 000000000000000Ch RW, RO, RW-L 64 bits Bit Access Reset Value RST/ PWR Description 63:39 RW 0000000h FLR, Uncore Reserved for Memory Base Address (RSVDRW) Must be set to 0 since addressing above 512 GB is not supported.
Processor Configuration Registers 2.8.12 IOBAR—I/O Base Address Register This register provides the Base offset of the I/O registers within Device 2. Bits 15:6 are programmable allowing the I/O Base to be located anywhere in 16bit I/O Address Space. Bits 2:1 are fixed and return zero; bit 0 is hardwired to a one indicating that 8 bytes of I/O space are decoded. Access to the 8Bs of I/O space is allowed in PM state D0 when I/O Enable (PCICMD bit 0) set.
Processor Configuration Registers 2.8.14 SID2—Subsystem Identification Register This register is used to uniquely identify the subsystem where the PCI device resides. B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 15:0 2.8.15 Access RW-O 0/2/0/PCI 2E–2Fh 0000h RW-O 16 bits Reset Value 0000h RST/ PWR Description Uncore Subsystem Identification (SUBID) This value is used to identify a particular subsystem. This field should be programmed by BIOS during boot-up.
Processor Configuration Registers 2.8.17 INTRLINE—Interrupt Line Register This 8-bit register is used to communicate interrupt line routing information. It is read/write and must be implemented by the device. POST software will write the routing information into this register as it initializes and configures the system. The value in this register tells which input of the system interrupt controller(s) the device's interrupt pin is connected to.
Processor Configuration Registers 2.8.20 MAXLAT—Maximum Latency Register The Integrated Graphics Device has no requirement for the settings of Latency Timers. B/D/F/Type: Address Offset: Reset Value: Access: Size: 2.8.21 0/2/0/PCI 3Fh 00h RO 8 bits Bit Access Reset Value RST/ PWR 7:0 RO 00h Uncore Description Maximum Latency Value (MLV) The IGD has no specific requirements for how often it needs to access the PCI bus.
Processor Configuration Registers 2.9 Device 2 IO Registers Table 2-12. Device 2 IO Register Address Map 2.9.1 Address Offset Register Symbol 0–3h Index 4–7h Data Register Name Reset Value Access MMIO Address Register 00000000h RW MMIO Data Register 00000000h RW Index—MMIO Address Register MMIO_INDEX: A 32 bit I/O write to this port loads the offset of the MMIO register or offset into the GTT that needs to be accessed. An I/O Read returns the current value of this register.
Processor Configuration Registers 2.10 PCI Device 6 Registers Table 2-13.
Processor Configuration Registers Table 2-13. PCI Device 6 Register Address Map (Sheet 2 of 2) 2.10.
Processor Configuration Registers 2.10.2 DID—Device Identification Register This register combined with the Vendor Identification register uniquely identifies any PCI device. B/D/F/Type: Address Offset: Reset Value: Access: Size: 2.10.3 0/6/0/PCI 2–3h 015Dh RO-FW 16 bits Bit Access Reset Value RST/ PWR Description 15:0 RO-FW 015Dh Uncore Device Identification Number MSB (DID_MSB) Identifier assigned to the processor root port (virtual PCI-to-PCI bridge, PCI Express Graphics port).
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 164 Access 0/6/0/PCI 4–5h 0000h RW, RO 16 bits 00h Reset Value RST/ PWR Description Uncore SERR# Message Enable (SERRE) This bit controls the root port’s SERR# messaging. The processor communicates the SERR# condition by sending an SERR message to the PCH. This bit, when set, enables reporting of non-fatal and fatal errors detected by the device to the Root Complex.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 2 Datasheet, Volume 2 Access RW 0/6/0/PCI 4–5h 0000h RW, RO 16 bits 00h Reset Value 0b RST/ PWR Description Uncore Bus Master Enable (BME) THis bit controls the ability of the PEG port to forward Memory Read/Write Requests in the upstream direction. 0 = This device is prevented from making memory requests to its primary bus.
Processor Configuration Registers 2.10.4 PCISTS—PCI Status Register This register reports the occurrence of error conditions associated with primary side of the "virtual" Host-PCI Express bridge embedded within the Root port.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 2.10.
Processor Configuration Registers 2.10.6 CC—Class Code Register This register identifies the basic function of the device, a more specific sub-class, and a register- specific programming interface. B/D/F/Type: Address Offset: Reset Value: Access: Size: 2.10.7 0/6/0/PCI 9–Bh 060400h RO 24 bits Bit Access Reset Value RST/ PWR 23:16 RO 06h Uncore Base Class Code (BCC) Indicates the base class code for this device. This code has the value 06h indicating a Bridge device.
Processor Configuration Registers 2.10.9 PBUSN—Primary Bus Number Register This register identifies that this "virtual" Host-PCI Express* bridge is connected to PCI bus 0. B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 7:0 2.10.10 Access RO 0/6/0/PCI 18h 00h RO 8 bits Reset Value 00h RST/ PWR Uncore Description Primary Bus Number (BUSN) Configuration software typically programs this field with the number of the bus on the primary side of the bridge.
Processor Configuration Registers 2.10.12 IOBASE—I/O Base Address Register This register controls the processor to PCI Express-G I/O access routing based on the following formula: IO_BASE ≤ address ≤ IO_LIMIT Only upper 4 bits are programmable. For the purpose of address decode address bits A[11:0] are treated as 0. Thus the bottom of the defined I/O address range will be aligned to a 4 KB boundary. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.10.
Processor Configuration Registers 2.10.14 SSTS—Secondary Status Register SSTS is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (that is, PCI Express-G side) of the "virtual" PCI-PCI bridge embedded within the processor.
Processor Configuration Registers 2.10.15 MBASE—Memory Base Address Register This register controls the processor to PCI Express-G non-prefetchable memory access routing based on the following formula: MEMORY_BASE ≤ address ≤ MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are readonly and return zeroes when read. This register must be initialized by the configuration software.
Processor Configuration Registers 2.10.16 MLIMIT—Memory Limit Address Register This register controls the processor to PCI Express-G non-prefetchable memory access routing based on the following formula: MEMORY_BASE ≤ address ≤ MEMORY_LIMIT The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are read-only and return zeroes when read. This register must be initialized by the configuration software.
Processor Configuration Registers 2.10.17 PMBASE—Prefetchable Memory Base Address Register This register in conjunction with the corresponding Upper Base Address register controls the processor to PCI Express-G prefetchable memory access routing based on the following formula: PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read/write and correspond to address bits A[31:20] of the 40-bit address.
Processor Configuration Registers 2.10.18 PMLIMIT—Prefetchable Memory Limit Address Register This register in conjunction with the corresponding Upper Limit Address register controls the processor to PCI Express-G prefetchable memory access routing based on the following formula: PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read/write and correspond to address bits A[31:20] of the 40-bit address.
Processor Configuration Registers 2.10.19 PMBASEU—Prefetchable Memory Base Address Upper Register The functionality associated with this register is present in the PEG design implementation.
Processor Configuration Registers 2.10.20 PMLIMITU—Prefetchable Memory Limit Address Upper Register The functionality associated with this register is present in the PEG design implementation.
Processor Configuration Registers 2.10.21 CAPPTR—Capabilities Pointer Register The capabilities pointer provides the address offset to the location of the first entry in this device's linked list of capabilities. B/D/F/Type: Address Offset: Reset Value: Access: Size: 2.10.22 0/6/0/PCI 34h 88h RO 8 bits Bit Access Reset Value RST/ PWR Description 7:0 RO 88h Uncore First Capability (CAPPTR1) The first capability in the list is the Subsystem ID and Subsystem Vendor ID Capability.
Processor Configuration Registers 2.10.23 INTRPIN—Interrupt Pin Register This register specifies which interrupt pin this device uses. B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit Access Reset Value RST/ PWR 7:3 RO 00h Uncore Reserved (RSVD) Uncore Interrupt Pin (INTPIN) As a multifunction device, the PCI Express device may specify any INTx (x=A,B,C,D) as its interrupt pin. The Interrupt Pin register tells which interrupt pin the device (or device function) uses.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Access Reset Value RST/ PWR 6 RW 0b Uncore Secondary Bus Reset (SRESET) Setting this bit triggers a hot reset on the corresponding PCI Express Port. This will force the LTSSM to transition to the Hot Reset state (using Recovery) from L0, L0s, or L1 states. 5 RO 0b Uncore Master Abort Mode (MAMODE) Does not apply to PCI Express. Hardwired to 0.
Processor Configuration Registers 2.10.25 PM_CAPID—Power Management Capabilities Register B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit Access 0/6/0/PCI 80–83h C8039001h RO, RO-V 32 bits Reset Value RST/ PWR Description 31:27 RO 19h Uncore PME Support (PMES) This field indicates the power states in which this device may indicate PME wake using PCI Express messaging. D0, D3hot & D3cold.
Processor Configuration Registers 2.10.26 PM_CS—Power Management Control/Status Register B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 182 0/6/0/PCI 84–87h 00000008h RO, RW 32 bits 000000h Bit Access Reset Value RST/ PWR 31:16 RO 0h 15 RO 0b Uncore PME Status (PMESTS) This bit indicates that this device does not support PME# generation from D3cold.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 1:0 Datasheet, Volume 2 Access RW 0/6/0/PCI 84–87h 00000008h RO, RW 32 bits 000000h Reset Value 00b RST/ PWR Description Uncore Power State (PS) This field indicates the current power state of this device and can be used to set the device into a new power state.
Processor Configuration Registers 2.10.27 SS_CAPID—Subsystem ID and Vendor ID Capabilities Register This capability is used to uniquely identify the subsystem where the PCI device resides. Because this device is an integrated part of the system and not an add-in device, it is anticipated that this capability will never be used. However, it is necessary because Microsoft will test for its presence. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.10.
Processor Configuration Registers 2.10.29 MSI_CAPID—Message Signaled Interrupts Capability ID Register When a device supports MSI it can generate an interrupt request to the processor by writing a predefined data item (a message) to a predefined memory address. The reporting of the existence of this capability can be disabled by setting MSICH (CAPL[0] @ 7Fh). In that case walking this linked list will skip this capability and instead go directly from the PCI PM capability to the PCI Express* capability.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 6:4 3:1 0 2.10.31 Access RW RO RW 0/6/0/PCI 92–93h 0000h RO, RW 16 bits 00h Reset Value 000b 000b 0b Description Uncore Multiple Message Enable (MME) System software programs this field to indicate the actual number of messages allocated to this device. This number will be equal to or less than the number actually requested. The encoding is the same as for the MMC field below.
Processor Configuration Registers 2.10.32 MD—Message Data Register B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 15:0 2.10.33 Access RW 0/6/0/PCI 98–99h 0000h RW 16 bits Reset Value 0000h RST/ PWR Description Uncore Message Data (MD) Base message data pattern assigned by system software and used to handle an MSI from the device. When the device must generate an interrupt request, it writes a 32-bit value to the memory address specified in the MA register.
Processor Configuration Registers 2.10.34 PEG_CAP—PCI Express-G Capabilities Register This register indicates PCI Express* device capabilities. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.10.35 0/6/0/PCI A2–A3h 0142h RO, RW-O 16 bits 0h Bit Access Reset Value 15:14 RO 0h 13:9 RO 00h RST/ PWR Description Reserved (RSVD) Uncore Interrupt Message Number (IMN) Not Applicable or Implemented. Hardwired to 0.
Processor Configuration Registers 2.10.36 DCTL—Device Control Register This register provides control for PCI Express* device specific capabilities. The error reporting enable bits are in reference to errors detected by this device, not error messages received across the link. The reporting of error messages (ERR_CORR, ERR_NONFATAL, ERR_FATAL) received by Root Port is controlled exclusively by Root Port Command Register.
Processor Configuration Registers 2.10.37 DSTS—Device Status Register This register reflects status corresponding to controls in the Device Control register. The error reporting bits are in reference to errors detected by this device, not errors messages received across the link.
Processor Configuration Registers 2.10.38 LCAP—Link Capabilities Register This register indicates PCI Express* device-specific capabilities. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Access 0/6/0/PCI AC–AFh 0521CC42h RO, RW-O, RO-V, RW-OV 32 bits 0h Reset Value RST/ PWR Description Uncore Port Number (PN) Indicates the PCI Express port number for the given PCI Express link. Matches the value in Element Self Description[31:24].
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 192 Access 0/6/0/PCI AC–AFh 0521CC42h RO, RW-O, RO-V, RW-OV 32 bits 0h Reset Value RST/ PWR Description 14:12 RO-V 100b Uncore L0s Exit Latency (L0SELAT) This field indicates the length of time this Port requires to complete the transition from L0s to L0.
Processor Configuration Registers 2.10.39 LCTL—Link Control Register This register allows control of PCI Express* link. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 0/6/0/PCI B0–B1h 0000h RO, RW, RW-V 16 bits 00h Bit Access Reset Value 15:12 RO 0h Reserved (RSVD) 0b Uncore Link Autonomous Bandwidth Interrupt Enable (LABIE) When set, this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 6 5 194 Access RW RW-V 0/6/0/PCI B0–B1h 0000h RO, RW, RW-V 16 bits 00h Reset Value 0b 0b RST/ PWR Description Uncore Common Clock Configuration (CCC) 0 = This component and the component at the opposite end of this Link are operating with asynchronous reference clock.
Processor Configuration Registers 2.10.40 LSTS—Link Status Register This register indicates PCI Express* link status.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 0/6/0/PCI B2–B3h 1001h RW1C, RO-V, RO 16 bits 0h Bit Access Reset Value 10 RO 0h 9:4 3:0 RO-V RO RST/ PWR Description Reserved (RSVD) 00h 0h Uncore Negotiated Link Width (NLW) This field indicates negotiated link width. This field is valid only when the link is in the L0, L0s, or L1 states (after link width negotiation is successfully completed).
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 16:15 Datasheet, Volume 2 Access RW-O 0/6/0/PCI B4–B7h 00040000h RW-O, RO 32 bits Reset Value 00b RST/ PWR Description Uncore Slot Power Limit Scale (SPLS) This field specifies the scale used for the Slot Power Limit Value. 00 = 1.0x 01 = 0.1x 10 = 0.01x 11 = 0.001x If this field is written, the link sends a Set_Slot_Power_Limit message.
Processor Configuration Registers 2.10.42 SLOTCTL—Slot Control Register Note: PCI Express* Hot-Plug is not supported on the processor.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 7:6 5 RO RO Reset Value 00b 0b RST/ PWR Description Uncore Reserved for Attention Indicator Control (AIC) If an Attention Indicator is implemented, writes to this field set the Attention Indicator to the written state.
Processor Configuration Registers 2.10.43 SLOTSTS—Slot Status Register This is a PCI Express* Slot related register. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Access Reset Value 15:9 RO 0h Reserved (RSVD) 0b Uncore Reserved for Data Link Layer State Changed (DLLSC) This bit is set when the value reported in the Data Link Layer Link Active field of the Link Status register is changed.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 4 Datasheet, Volume 2 Access RO 0/6/0/PCI BA–BBh 0000h RO, RO-V, RW1C 16 bits 00h Reset Value 0b RST/ PWR Description Uncore Reserved for Command Completed (CC) If Command Completed notification is supported (as indicated by No Command Completed Support field of Slot Capabilities Register), this bit is set when a hot-plug command has completed and the Hot-Plug Controller is ready to
Processor Configuration Registers 2.10.44 RCTL—Root Control Register This register allows control of PCI Express* Root Complex specific parameters. The system error control bits in this register determine if corresponding SERRs are generated when our device detects an error (reported in this device's Device Status register) or when an error message is received across the link. Reporting of SERR as controlled by these bits takes precedence over the SERR Enable in the PCI Command Register.
Processor Configuration Registers 2.11 PCI Device 6 Extended Configuration Registers Table 2-14.
Processor Configuration Registers 2.11.1 PVCCAP1—Port VC Capability Register 1 This register describes the configuration of PCI Express* Virtual Channels associated with this port. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.11.
Processor Configuration Registers 2.11.3 PVCCTL—Port VC Control Register B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Access Reset Value 15:4 RO 0h 3:1 0 2.11.4 0/6/0/MMR 10C–10Dh 0000h RW, RO 16 bits 000h RW Description Reserved (RSVD) 000b RO RST/ PWR 0b Uncore VC Arbitration Select (VCAS) This field will be programmed by software to the only possible value as indicated in the VC Arbitration Capability field.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 7:0 206 Access RO 0/6/0/MMR 110–113h 00000001h RO 32 bits 00h Reset Value 01h RST/ PWR Description Uncore Port Arbitration Capability (PAC) Indicates types of Port Arbitration supported by the VC resource.
Processor Configuration Registers 2.11.5 VC0RCTL—VC0 Resource Control Register This register controls the resources associated with PCI Express* Virtual Channel 0. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 0/6/0/MMR 114–117h 800000FFh RO, RW 32 bits 000h Bit Access Reset Value RST/ PWR Description 31 RO 1b Uncore VC0 Enable (VC0E) For VC0 this is hardwired to 1 and read only as VC0 can never be disabled.
Processor Configuration Registers 2.11.6 VC0RSTS—VC0 Resource Status Register This register reports the Virtual Channel specific status. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.11.7 0/6/0/MMR 11A–11Bh 0002h RO-V 16 bits 0000h Bit Access Reset Value 15:2 RO 0h Reserved (RSVD) VC0 Negotiation Pending (VC0NP) 0 = The VC negotiation is complete. 1 = The VC resource is still in the process of negotiation (initialization or disabling).
Processor Configuration Registers 2.11.8 ESD—Element Self Description Register This register provides information about the root complex element containing this Link Declaration Capability.
Processor Configuration Registers 2.11.9 LE1D—Link Entry 1 Description Register This register provides the first part of a Link Entry that declares an internal link to another Root Complex Element. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 31:24 RO Reset Value 00h 23:16 RW-O 00h 15:2 RO 0h 1 RO 0b 0 2.11.
Processor Configuration Registers 2.11.11 LE1AH—Link Entry 1 Address Register This register provides the second part of a Link Entry that declares an internal link to another Root Complex Element. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Access Reset Value 31:8 RO 0h 7:0 2.11.
Processor Configuration Registers 2.11.13 APICLIMIT—APIC Base Address Limit Register B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.11.14 0/6/0/MMR 244–247h 00000000h RW 32 bits 000000h Bit Access Reset Value 31:12 RO 0h 11:4 RW 00h 3:0 RO 0h Description Reserved (RSVD) Uncore APIC Base Address (APICLIMIT): Bits 19:12 of the APIC Limit Bits 31:20 are assumed to be FECh. Bits 0:11 are don't care for address decode.
Processor Configuration Registers 2.11.15 PEGTST—PCI Express* Test Modes Register B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 0/6/0/MMR D0C–D0Fh 00000000h RO-FW, RW 32 bits 0000000h Bit Access Reset Value 31:21 RO 0h 20 RO-FW RST/ PWR Description Reserved (RSVD) 0b Uncore PEG Lane Reversal Strap Status (LANEREVSTS) This register bit reflects the status of the PEG lane reversal strap. The PEGLaneReversal strap is mirrored in this register bit.
Processor Configuration Registers 2.11.17 BGFCTL3—BGF Control 3 Register B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 214 0/6/0/MMR D6C–D6Fh 400204E0h RW 32 bits 0000h Bit Access Reset Value RST/ PWR 31 RW 0b Uncore Fclock Bubble Enable (FBEN) This bit disable Bubble generator on Fclk side of BGF. 0 = Disabled 1 = Enabled. Uncore Lclock Bubble Enable (LBEN) This bit enable Bubble generator on Lclk side of BGF 0 = Disabled 1 = Enabled.
Processor Configuration Registers 2.11.18 EQPRESET1_2—Equalization Preset 1/2 Register This register contains coefficients for Preset 1 and 2. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.11.19 0/6/0/MMR DC0–DC3h 3400FBC0h RW 32 bits 0h Bit Access Reset Value RST/ PWR 31:30 RO 0h 29:24 RW 34h Uncore Preset 2 Cursor Coefficient (CURSOR2) Cursor coefficient for Preset 2.
Processor Configuration Registers 2.11.20 EQPRESET6_7—Equalization Preset 6/7 Register This register contains coefficients for Preset 6 and 7. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.11.21 0/6/0/MMR DCC–DCFh 36200E06h RW 32 bits 0h Bit Access Reset Value 31:6 RO 0h 5:0 RW 06h Description Reserved (RSVD) Uncore Preset 6 Precursor Coefficient (PRECUR6): Precursor coefficient for Preset 6.
Processor Configuration Registers 2.12 Direct Media Interface Base Address Registers (DMIBAR) Table 2-15.
Processor Configuration Registers Table 2-15. DMIBAR Register Address Map (Sheet 2 of 2) Address Offset 2.12.
Processor Configuration Registers 2.12.2 DMIPVCCAP1—DMI Port VC Capability Register 1 This register describes the configuration of PCI Express* Virtual Channels associated with this port. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.12.
Processor Configuration Registers 2.12.4 DMIPVCCTL—DMI Port VC Control Register B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.12.5 0/0/0/DMIBAR C–Dh 0000h RW, RO 16 bits 000h Bit Access Reset Value 15:4 RO 0h Description Reserved (RSVD) 3:1 RW 000b Uncore VC Arbitration Select (VCAS) This field will be programmed by software to the only possible value as indicated in the VC Arbitration Capability field.
Processor Configuration Registers 2.12.6 DMIVC0RCTL—DMI VC0 Resource Control Register This register controls the resources associated with PCI Express* Virtual Channel 0. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 0/0/0/DMIBAR 14–17h 8000007Fh RO, RW 32 bits 00000h Bit Access Reset Value RST/ PWR Description 31 RO 1b Uncore Virtual Channel 0 Enable (VC0E) For VC0, this is hardwired to 1 and read only as VC0 can never be disabled.
Processor Configuration Registers 2.12.7 DMIVC0RSTS—DMI VC0 Resource Status Register This register reports the Virtual Channel specific status. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.12.8 0/0/0/DMIBAR 1A–1Bh 0002h RO-V 16 bits 0000h Bit Access Reset Value 15:2 RO 0h Reserved (RSVD) Virtual Channel 0 Negotiation Pending (VC0NP) 0 = The VC negotiation is complete. 1 = The VC resource is still in the process of negotiation (initialization or disabling).
Processor Configuration Registers 2.12.9 DMIVC1RCTL—DMI VC1 Resource Control Register This register controls the resources associated with PCI Express* Virtual Channel 1.
Processor Configuration Registers 2.12.10 DMIVC1RSTS—DMI VC1 Resource Status Register This register reports the Virtual Channel specific status. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.12.11 0/0/0/DMIBAR 26–27h 0002h RO-V 16 bits 0000h Bit Access Reset Value 15:2 RO 0h Reserved (RSVD) Virtual Channel 1 Negotiation Pending (VC1NP) 0 = The VC negotiation is complete. 1 = The VC resource is still in the process of negotiation (initialization or disabling).
Processor Configuration Registers 2.12.12 DMIVCPRCTL—DMI VCp Resource Control Register This register controls the resources associated with the DMI Private Channel (VCp).
Processor Configuration Registers 2.12.13 DMIVCPRSTS—DMI VCp Resource Status Register This register reports the Virtual Channel specific status. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.12.14 0/0/0/DMIBAR 32–33h 0002h RO-V 16 bits 0000h Bit Access Reset Value 15:2 RO 0h Reserved (RSVD) Virtual Channel private Negotiation Pending (VCPNP) 0 = The VC negotiation is complete. 1 = The VC resource is still in the process of negotiation (initialization or disabling).
Processor Configuration Registers 2.12.15 DMIVCMRCTL—DMI VCm Resource Control Register B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Access 0/0/0/DMIBAR 38–3Bh 07000080h RW, RO 32 bits 00000h Reset Value 31 RW 0b 30:27 RO 0h 26:24 RW 111b 23:8 RO 0h 7:0 Datasheet, Volume 2 RO 80h RST/ PWR Description Uncore Virtual Channel enable (VCMEN) 0 = Virtual Channel is disabled. 1 = Virtual Channel is enabled. See exceptions below.
Processor Configuration Registers 2.12.16 DMIVCMRSTS—DMI VCm Resource Status Register B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.12.17 0/0/0/DMIBAR 3E–3Fh 0002h RO-V 16 bits 0000h Bit Access Reset Value 15:2 RO 0h Reserved (RSVD) Virtual Channel Negotiation Pending (VCNEGPND) 0 = The VC negotiation is complete. 1 = The VC resource is still in the process of negotiation (initialization or disabling). Software may use this bit when enabling or disabling the VC.
Processor Configuration Registers 2.12.18 DMIESD—DMI Element Self Description Register This register provides information about the root complex element containing this Link Declaration Capability.
Processor Configuration Registers 2.12.19 DMILE1D—DMI Link Entry 1 Description Register This register provides the first part of a Link Entry which declares an internal link to another Root Complex Element.
Processor Configuration Registers 2.12.20 DMILE1A—DMI Link Entry 1 Address Register This register provides the second part of a Link Entry that declares an internal link to another Root Complex Element. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.12.
Processor Configuration Registers 2.12.22 DMILE2D—DMI Link Entry 2 Description Register This register provides the first part of a Link Entry that declares an internal link to another Root Complex Element.
Processor Configuration Registers 2.12.23 DMILE2A—DMI Link Entry 2 Address Register This register provides the second part of a Link Entry that declares an internal link to another Root Complex Element. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.12.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Access Reset Value RST/ PWR 11:10 RO 11b Uncore Active State Link PM Support (ASLPMS) L0s & L1 entry supported. 9:4 RO 04h Uncore Max Link Width (MLW) This field indicates the maximum number of lanes supported for this link. Uncore Max Link Speed (MLS) This Reset Value reflects gen1. Later the field may be changed by BIOS to allow gen2 subject to Fuse enabled.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Reset Value RST/ PWR Description 4 RW 0b Uncore Link Disable (LD) 0 = Normal operation 1 = link is disabled. Forces the LTSSM to transition to the Disabled state (using Recovery) from L0, L0s, or L1 states. Link retraining happens automatically on 0 to 1 transition, just like when coming out of reset.
Processor Configuration Registers 2.12.27 LCTL2—Link Control 2 Register B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 15:12 11 10 236 Access RWS RWS RWS 0/0/0/DMIBAR 98–99h 0002h RWS, RWS-V 16 bits Reset Value 0000b 0b 0b RST/ PWR Description Powergood Compliance De-emphasis (ComplianceDeemphasis) For 8 GT/s Data Rate: This field sets the Transmitter Preset level in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 9:7 6 Datasheet, Volume 2 Access RWS-V RWS 0/0/0/DMIBAR 98–99h 0002h RWS, RWS-V 16 bits Reset Value 000b 0b RST/ PWR Description Powergood Transmit Margin (txmargin) This field controls the value of the non-deemphasized voltage level at the Transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit Access Reset Value RST/ PWR 5 RWS 0b Powergood Hardware Autonomous Speed Disable (HASD) When set to 1b this bit disables hardware from changing the link speed for reasons other than attempting to correct unreliable link operation by reducing link speed.
Processor Configuration Registers 2.13 MCHBAR Registers in Memory Controller—Channel 0 Registers Table 2-16.
Processor Configuration Registers 2.13.1 TC_DBP_C0—Timing of DDR – Bin Parameters Register This register defines the BIN timing parameters for safe logic – tRCD, tRP, tCL, tWCL and tRAS.
Processor Configuration Registers 2.13.2 TC_RAP_C0—Timing of DDR – Regular Access Parameters Register Thie register is for the regular timing parameters in DCLK cycles. B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 31:30 Access RW-L 0/0/0/MCHBAR MC0 4004–4007h 86104344h RW-L 32 bits Reset Value 10b RST/ PWR Description Uncore 1n 2N or 3N selection (CMD_stretch) This field defines the operation mode of the command.
Processor Configuration Registers 2.13.3 SC_IO_LATENCY_C0—IO Latency configuration Register This register identifies the I/O latency per rank, and I/O compensation (global). B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.13.
Processor Configuration Registers 2.13.5 PM_PDWN_config_C0–Power-down Configuration Register This register defines the power-down (CKE-off) operation – power-down mode, idle timer and global / per rank decision. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 0/0/0/MCHBAR MC0 40B0–40B3h 00000000h RW-L 32 bits 00000h Bit Access Reset Value 31:13 RO 0h Reserved (RSVD) 0b Global power-down (GLPDN) 1 = When this bit is set, the power-down decision is global for channel.
Processor Configuration Registers 2.13.6 TC_RFP_C0—Refresh Parameters Register This register provides the refresh parameters. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Access Reset Value 31:18 RO 0h 17:16 2.13.7 0/0/0/MCHBAR MC0 4294–4297h 0000980Fh RW-L 32 bits 0000h RW-L RST/ PWR Description Reserved (RSVD) 00b Uncore Double Refresh Control (DOUBLE_REFRESH_CONTROL) This field will allow the double self refresh enable/disable.
Processor Configuration Registers 2.14 MCHBAR Registers in Memory Controller – Channel 1 Table 2-17. MCHBAR Registers in Memory Controller – Channel 1 Register Address Map Address Register Symbol 0–43FFh RSVD 4400–4403h TC_DBP_C1 TC_RAP_C1 4404–4407h 2.14.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 2.14.2 Access 0/0/0/MCHBAR MC1 4400–4403h 00146666h RW-L 32 bits 00h Reset Value RST/ PWR Description 11:8 RW-L 6h Uncore CAS latency in DCLK cycles (tCL) Delay from CAS command to data out of DDR pins. This does not define the sample point in the I/O.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: 2.14.3 0/0/0/MCHBAR MC1 4404–4407h 86104344h RW-L 32 bits Bit Access Reset Value RST/ PWR 15:12 RW-L 4h Uncore tWTR in DCLK cycles (tWTR) Delay from internal WR transaction to internal RD transaction. The minimum delay is 4 DCLK cycles, whereas the maximum delay is 8 DCLK cycles. 11:8 RW-L 3h Uncore tCKE in DCLK cycles (tCKE) CKE minimum pulse width in DCLK cycles.
Processor Configuration Registers 2.14.4 PM_PDWN_config_C1—Power-down Configuration Register This register defines the power-down (CKE-off) operation – power-down mode, idle timer and global / per rank decision.
Processor Configuration Registers 2.14.5 TC_RFP_C1—Refresh Parameters Register This register provides refresh parameters. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 0/0/0/MCHBAR MC1 4694–4697h 0000980Fh RW-L 32 bits 0000h Bit Access Reset Value 31:18 RO 0h 17:16 RW-L 00b RST/ PWR Description Reserved (RSVD) Uncore Double Refresh Control (DOUBLE_REFRESH_CONTROL) This field will allow the double self refresh enable/disable.
Processor Configuration Registers 2.14.6 TC_RFTP_C1—Refresh Timing Parameters Register Thie register provides refresh timing parameters. B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 2.14.
Processor Configuration Registers 2.15 MCHBAR Registers in Memory Controller – Integrated Memory Peripheral Hub (IMPH) Table 2-18. MCHBAR Registers in Memory Controller –Integrated Memory Peripheral Hub (IMPH) Register Address Map Address Offset 2.15.
Processor Configuration Registers 2.15.2 CRDTCTL4—Credit Control 4 Register This register will have the minimum Read Return Tracker credits for each of the PEG/DMI/GSA streams. B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit Access Reset Value RST/ PWR 31:6 RO 0h Uncore Reserved (RSVD) Uncore Read Return Tracker Shared Credits (RDRT_SHRD) This field indicates the number of credits that are in the RDRTRN shared pool.
Processor Configuration Registers 2.16 MCHBAR Registers in Memory Controller – Common Table 2-19. MCHBAR Registers in Memory Controller – Common Register Address Map 2.16.
Processor Configuration Registers 2.16.2 MAD_DIMM_ch0—Address Decode Channel 0 Register This register defines channel characteristics – number of DIMMs, number of ranks, size, interleave options.
Processor Configuration Registers 2.16.3 MAD_DIMM_ch1—Address Decode Channel 1 Register This register defines channel characteristics – number of DIMMs, number of ranks, size, interleave options.
Processor Configuration Registers 2.16.4 PM_SREF_config—Self Refresh Configuration Register This is a self refresh mode control register – defines if and when DDR can go into SR.
Processor Configuration Registers 2.17 Memory Controller MMIO Registers Broadcast Group Registers Table 2-20.
Processor Configuration Registers 2.17.1 PM_PDWN_config—Power-down Configuration Register This register defines the power-down (CKE-off) operation – power-down mode, idle timer and global / per rank decision. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 258 0/0/0/MCHBAR_MCBCAST 4CB0–4CB3h 00000000h RW-L 32 bits 00000h Bit Access Reset Value 31:13 RO 0h 12 RW-L 0b RST/ PWR Description Reserved (RSVD) Uncore Global power-down (GLPDN) Global Power Down.
Processor Configuration Registers 2.17.2 PM_CMD_PWR—Power Management Command Power Register This register defines the power contribution of each command – ACT+PRE, CAS-read, and CAS write. Assumption is that the ACT is always followed by a PRE (although not immediately), and REF commands are issued in a fixed rate and there is no need to count them. The register has 3 8-bit fields.
Processor Configuration Registers 2.18 Integrated Graphics VTd Remapping Engine Registers Table 2-21.
Processor Configuration Registers Table 2-21. Integrated Graphics VTd Remapping Engine Register Address Map (Sheet 2 of 2) Address Offset Register Symbol AC–AFh IEUADDR_REG B0–B7h RSVD B8–BFh IRTA_REG C0–FFh RSVD 2.18.
Processor Configuration Registers 2.18.2 CAP_REG—Capability Register This register reports general remapping hardware capabilities. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Access Reset Value 63:56 RO 0h 55 RO 1b Uncore DMA Read Draining (DRD) 0 = Hardware does not support draining of DMA read requests. 1 = Hardware supports draining of DMA read requests.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 33:24 23 22 Access RO RO RO 0/0/0/GFXVTBAR 8–Fh 00C0000020E60262h RO 64 bits 000h Reset Value 020h 1b 1b 21:16 RO 100110b 15:13 RO 0h Datasheet, Volume 2 RST/ PWR Description Uncore Fault-recording Register offset (FRO) This field specifies the location to the first fault recording register relative to the register base address of this remapping hardware unit.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 12:8 264 Access RO 0/0/0/GFXVTBAR 8–Fh 00C0000020E60262h RO 64 bits 000h Reset Value 00010b RST/ PWR Description Uncore Supported Adjusted Guest Address Widths (SAGAW) This 5-bit field indicates the supported adjusted guest address widths (which in turn represents the levels of page-table walks for the 4 KB base page size) supported by the hardware implementation.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Reset Value RST/ PWR Description 4 RO 0b Uncore Required Write-Buffer Flushing (RWBF) 0 = No write-buffer flushing is needed to ensure changes to memory-resident structures are visible to hardware. 1 = Software must explicitly flush the write buffers to ensure updates made to memory-resident remapping structures are visible to hardware.
Processor Configuration Registers 2.18.3 ECAP_REG—Extended Capability Register This Register reports remapping hardware extended capabilities.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 0 2.18.4 Access 0/0/0/GFXVTBAR 10–17h 0000000000F0101Ah RO, RO-V 64 bits 00000000000h Reset Value RO 0b RST/ PWR Description Uncore Coherency (C) This field indicates if hardware access to the root, context, pagetable and interrupt-remap structures are coherent (snooped) or not. 0 = Hardware accesses to remapping structures are noncoherent.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 30 29 28 268 Access WO RO RO 0/0/0/GFXVTBAR 18–1Bh 00000000h RO, WO 32 bits 000000h Reset Value 0b 0b 0b RST/ PWR Description Uncore Set Root Table Pointer (SRTP) Software sets this field to set/update the root-entry table pointer used by hardware. The root-entry table pointer is specified through the Root-entry Table Address (RTA_REG) register.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 27 26 25 Datasheet, Volume 2 Access RO WO WO 0/0/0/GFXVTBAR 18–1Bh 00000000h RO, WO 32 bits 000000h Reset Value 0b 0b 0b RST/ PWR Description Uncore Write Buffer Flush (WBF) This bit is valid only for implementations requiring write buffer flushing. Software sets this field to request that hardware flush the RootComplex internal write buffers.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 270 Access 0/0/0/GFXVTBAR 18–1Bh 00000000h RO, WO 32 bits 000000h Reset Value 24 WO 0b 23:0 RO 0h RST/ PWR Description Uncore Set Interrupt Remap Table Pointer (SIRTP) This field is valid only for implementations supporting interruptremapping. Software sets this field to set/update the interrupt remapping table pointer used by hardware.
Processor Configuration Registers 2.18.5 GSTS_REG—Global Status Register This register reports general remapping hardware status. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Access Reset Value RST/ PWR 31 RO-V 0b Uncore Translation Enable Status (TES) This field indicates the status of DMA-remapping hardware.
Processor Configuration Registers 2.18.6 RTADDR_REG—Root-Entry Table Address Register This register providing the base address of root-entry table.
Processor Configuration Registers 2.18.7 CCMD_REG—Context Command Register This register manages context cache. The act of writing the uppermost byte of the CCMD_REG with the ICC field set causes the hardware to perform the context-cache invalidation.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Reset Value RST/ PWR Description Uncore Context Actual Invalidation Granularity (CAIG) Hardware reports the granularity at which an invalidation request was processed through the CAIG field at the time of reporting invalidation completion (by clearing the ICC field). The following are the encodings for this field: 00 = Reserved. 01 = Global Invalidation performed.
Processor Configuration Registers 2.18.8 FSTS_REG—Fault Status Register This register indicates the various error status. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 0/0/0/GFXVTBAR 34–37h 00000000h RO, ROS-V, RW1CS 32 bits 00000h Bit Access Reset Value 31:16 RO 0h Description Reserved (RSVD) ROS-V 00h 7 RO 0h Reserved (RSVD) 0b Uncore Invalidation Time-out Error (ITE) Hardware detected a Device-IOTLB invalidation completion time-out.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 2 1 0 276 Access RO ROS-V RW1CS 0/0/0/GFXVTBAR 34–37h 00000000h RO, ROS-V, RW1CS 32 bits 00000h Reset Value 0b 0b 0b RST/ PWR Description Uncore Advanced Fault Overflow (AFO) Hardware sets this field to indicate advanced fault log overflow condition. At this time, a fault event is generated based on the programming of the Fault Event Control register.
Processor Configuration Registers 2.18.9 FECTL_REG—Fault Event Control Register This register specifies the fault event interrupt message control bits. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 31 Datasheet, Volume 2 Access RW 0/0/0/GFXVTBAR 38–3Bh 80000000h RW, RO-V 32 bits 00000000h Reset Value 1b 30 RO-V 0h 29:0 RO 0h RST/ PWR Description Uncore Interrupt Mask (IM) 0 = No masking of interrupt.
Processor Configuration Registers 2.18.10 FEDATA_REG—Fault Event Data Register This register specifies the interrupt message data. B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 2.18.11 Access 0/0/0/GFXVTBAR 3C–3Fh 00000000h RW 32 bits Reset Value RST/ PWR Description 31:16 RW 0000h Uncore Extended Interrupt Message Data (EIMD): This field is valid only for implementations supporting 32-bit interrupt data fields.
Processor Configuration Registers 2.18.13 AFLOG_REG—Advanced Fault Log Register This register specifies the base address of the memory-resident fault-log region. This register is treated as RsvdZ for implementations not supporting advanced translation fault logging (AFL field reported as 0 in the Capability register).
Processor Configuration Registers 2.18.14 PMEN_REG—Protected Memory Enable Register This register enables the DMA-protected memory regions setup through the PLMBASE, PLMLIMT, PHMBASE, PHMLIMIT registers. This register is always treated as RO for implementations not supporting protected memory regions (PLMR and PHMR fields reported as Clear in the Capability register). Protected memory regions may be used by software to securely initialize remapping structures in memory.
Processor Configuration Registers 2.18.15 PLMBASE_REG—Protected Low-Memory Base Register This register sets up the base address of DMA-protected low-memory region below 4 GB. This register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. This register is always treated as RO for implementations not supporting protected low memory region (PLMR field reported as Clear in the Capability register).
Processor Configuration Registers 2.18.16 PLMLIMIT_REG—Protected Low-Memory Limit Register This register sets up the limit address of DMA-protected low-memory region below 4 GB. This register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. This register is always treated as RO for implementations not supporting protected low memory region (PLMR field reported as Clear in the Capability register).
Processor Configuration Registers 2.18.17 PHMBASE_REG—Protected High-Memory Base Register This register sets up the base address of DMA-protected high-memory region. This register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. This register is always treated as RO for implementations not supporting protected high memory region (PHMR field reported as Clear in the Capability register).
Processor Configuration Registers 2.18.18 PHMLIMIT_REG—Protected High-Memory Limit Register This register sets up the limit address of DMA-protected high-memory region. This register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. This register is always treated as RO for implementations not supporting protected high memory region (PHMR field reported as Clear in the Capability register).
Processor Configuration Registers 2.18.19 IQH_REG—Invalidation Queue Head Register This register indicates the invalidation queue head. This register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.18.
Processor Configuration Registers 2.18.21 IQA_REG—Invalidation Queue Address Register This register configures the base address and size of the invalidation queue. This register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register.
Processor Configuration Registers 2.18.23 IECTL_REG—Invalidation Event Control Register This register specifies the invalidation event interrupt control bits. This register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register.
Processor Configuration Registers 2.18.24 IEDATA_REG—Invalidation Event Data Register This register specifies the Invalidation Event interrupt message data. This register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register. B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 2.18.
Processor Configuration Registers 2.18.26 IEUADDR_REG—Invalidation Event Upper Address Register This register specifies the Invalidation Event interrupt message upper address. B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 31:0 2.18.
Processor Configuration Registers 2.18.28 IVA_REG—Invalidate Address Register This register provides the DMA address whose corresponding IOTLB entry needs to be invalidated through the corresponding IOTLB Invalidate register. This register is a write-only register.
Processor Configuration Registers 2.18.29 IOTLB_REG—IOTLB Invalidate Register This register invalidates IOTLB. The act of writing the upper byte of the IOTLB_REG with IVT field set causes the hardware to perform the IOTLB invalidation.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Reset Value RST/ PWR Description Uncore IOTLB Actual Invalidation Granularity (IAIG) Hardware reports the granularity at which an invalidation request was processed through this field when reporting invalidation completion (by clearing the IVT field). The following are the encodings for this field. 00 = Reserved.
Processor Configuration Registers 2.18.30 FRCDL_REG—Fault Recording Low Register This register records fault information when primary fault logging is active. Hardware reports the number and location of fault recording registers through the Capability register. This register is relevant only for primary fault logging. This register is sticky and can be cleared only through power good reset or by software clearing the RW1C fields by writing a 1.
Processor Configuration Registers 2.18.31 FRCDH_REG—Fault Recording High Register This register records fault information when primary fault logging is active. Hardware reports the number and location of fault recording registers through the Capability register. This register is relevant only for primary fault logging. This register is sticky and can be cleared only through power good reset or by software clearing the RW1C fields by writing a 1.
Processor Configuration Registers 2.18.32 VTPOLICY—DMA Remap Engine Policy Control Register This register contains all the policy bits related to the DMA remap engine.
Processor Configuration Registers 2.19 PCU MCHBAR Registers Table 2-22.
Processor Configuration Registers 2.19.1 MEM_TRML_ESTIMATION_CONFIG—Memory Thermal Estimation Configuration Register This register contains configuration regarding VTS temperature estimation calculations that are done by PCODE.
Processor Configuration Registers 2.19.2 MEM_TRML_THRESHOLDS_CONFIG—Memory Thermal Thresholds Configuration Register This register is used to describe the thresholds of the memory thermal management in the memory controller. The warm threshold defines when self-refresh is at double data rate. Throttling can also be applied at this threshold based on the configuration in the memory controller. The hot threshold defines the threshold at which severe thermal throttling will occur.
Processor Configuration Registers 2.19.3 MEM_TRML_STATUS_REPORT—Memory Thermal Status Report Register This register reports the thermal status of DRAM.
Processor Configuration Registers 2.19.4 MEM_TRML_TEMPERATURE_REPORT—Memory Thermal Temperature Report Register This register is used to report the thermal status of the memory. The channel max temperature field is used to report the maximal temperature of all ranks. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.19.
Processor Configuration Registers 2.19.6 GT_PERF_STATUS—GT Performance Status Register This register provides the P-state encoding for the Secondary Power Plane’s current PLL frequency and the current VID. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.19.
Processor Configuration Registers 2.19.8 RP_STATE_CAP—RP State Capability Register This register contains the maximum base frequency capability for the Integrated Graphics Engine (GT). B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.19.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: 0/0/0/MCHBAR PCU 5C20–5C23h 00000000h RW 32 bits Bit Access Reset Value 20:19 RW 00000000h 18 RW 00000000h Uncore pp1_clipped_pl1 Set if the PP1 (GT) frequency requested was clipped by PL1 (POWER_LIMIT_1) power limiting algorithm. 17 RW 00000000h Uncore pp1_clipped_thermals Set if the PP1 (GT) frequency requested was clipped by internal Thermal Throttling algorithm.
Processor Configuration Registers 2.19.10 PCU_MMIO_FREQ_CLIPPING_CAUSE_LOG Register This register is the log of the frequency clipping cause in MMIO for both Power plane 0 (IA) and Power plane 1 (GT). The bit definitions are the same as in PCU_MMIO_FREQ_CLIPPING_CAUSE_STATUS register; the processor will constantly ‘or’ in the status to give a log of any clipping since the last clear. Software can clear the log by writing zeros to this register.
Processor Configuration Registers B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Datasheet, Volume 2 Access 0/0/0/MCHBAR PCU 5C24-5C27h 00000000h RW 32 bits Reset Value RST/ PWR Uncore Description pp0_clipped_non_turbo Set if the PP0 (IA) frequency requested by OS was clipped, but current frequency is lower than MAX_NON_TURBO.
Processor Configuration Registers 2.19.11 SSKPD—Sticky Scratchpad Data Register This register holds 64 writable bits with no functionality behind them. It is for the convenience of BIOS and graphics drivers. B/D/F/Type: Address Offset: Reset Value: Access: Size: 0/0/0/MCHBAR PCU 5D10–5D17h 0000000000000000h RWS, RW 64 bits Bit Access Reset Value RST/ PWR 63:32 RWS 00000000h Powergood Scratchpad Data (SKPD) 2 WORDs of data storage.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 13:8 Access RWS 0/0/0/MCHBAR PCU 5D10–5D17h 0000000000000000h RWS, RW 64 bits Reset Value 000000b RST/ PWR Powergood Description Self Refresh and MDLL Latency Time (WM1) This field provides the number of microseconds to access memory if memory is in Self Refresh and MDLL is turned off (0.5 us granularity). 00h = 0 us 01h = 0.5 us 02h = 1 us ... 3Fh = 31.
Processor Configuration Registers 2.20 PXPEPBAR Registers Table 2-23. PXPEPBAR Address Map Address Offset 2.20.1 Register Symbol 0–13h RSVD 14–17h EPVC0RCTL 18–9Fh RSVD Register Name Reset Value Reserved EP VC 0 Resource Control Access 0h RO 800000FFh RO, RW — — Reserved EPVC0RCTL—EP VC 0 Resource Control Register This register controls the resources associated with Egress Port Virtual Channel 0.
Processor Configuration Registers 2.21 Default PEG/DMI VTd Remapping Engine Registers Table 2-24.
Processor Configuration Registers Table 2-24. Default PEG/DMI VTd Remapping Engine Register Address Map (Sheet 2 of 2) 2.21.
Processor Configuration Registers 2.21.2 CAP_REG—Capability Register This register reports general remapping hardware capabilities. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 0/0/0/VC0PREMAP 8–Fh 00C9008020660262h RO 64 bits 000h Bit Access Reset Value 63:56 RO 0h 55 RO 1b Uncore DMA Read Draining (DRD) 0 = Hardware does not support draining of DMA read requests. 1 = Hardware supports draining of DMA read requests.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 33:24 23 22 312 Access RO RO RO 0/0/0/VC0PREMAP 8–Fh 00C9008020660262h RO 64 bits 000h Reset Value 020h 0b 1b 21:16 RO 100110b 15:13 RO 0h RST/ PWR Description Uncore Fault-recording Register offset (FRO) This field specifies the location to the first fault recording register relative to the register base address of this remapping hardware unit.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 12:8 Datasheet, Volume 2 Access RO 0/0/0/VC0PREMAP 8–Fh 00C9008020660262h RO 64 bits 000h Reset Value 00010b RST/ PWR Description Uncore Supported Adjusted Guest Address Widths (SAGAW) This 5-bit field indicates the supported adjusted guest address widths (which in turn represents the levels of page-table walks for the 4 KB base page size) supported by the hardware implementation.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Reset Value RST/ PWR Description 4 RO 0b Uncore Required Write-Buffer Flushing (RWBF) 0 = Indicates no write-buffer flushing is needed to ensure changes to memory-resident structures are visible to hardware. 1 = Indicates software must explicitly flush the write buffers to ensure updates made to memory-resident remapping structures are visible to hardware.
Processor Configuration Registers 2.21.3 ECAP_REG—Extended Capability Register This register reports remapping hardware extended capabilities.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 0 2.21.4 Access 0/0/0/VC0PREMAP 10–17h 0000000000F010DAh RO-V, RO 64 bits 00000000000h Reset Value RO 0b RST/ PWR Description Uncore Coherency (C) This field indicates if hardware access to the root, context, pagetable and interrupt-remap structures are coherent (snooped) or not. 0 = Hardware accesses to remapping structures are noncoherent.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 30 29 28 Datasheet, Volume 2 Access WO RO RO 0/0/0/VC0PREMAP 18–1Bh 00000000h RO, WO 32 bits 000000h Reset Value 0b 0b 0b RST/ PWR Description Uncore Set Root Table Pointer (SRTP) Software sets this field to set/update the root-entry table pointer used by hardware. The root-entry table pointer is specified through the Root-entry Table Address (RTA_REG) register.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 27 26 25 318 Access RO WO WO 0/0/0/VC0PREMAP 18–1Bh 00000000h RO, WO 32 bits 000000h Reset Value 0b 0b 0b RST/ PWR Description Uncore Write Buffer Flush (WBF) This bit is valid only for implementations requiring write buffer flushing. Software sets this field to request that hardware flush the RootComplex internal write buffers.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Datasheet, Volume 2 Access 0/0/0/VC0PREMAP 18–1Bh 00000000h RO, WO 32 bits 000000h Reset Value 24 WO 0b 23:0 RO 0h RST/ PWR Description Uncore Set Interrupt Remap Table Pointer (SIRTP) This field is valid only for implementations supporting interruptremapping. Software sets this field to set/update the interrupt remapping table pointer used by hardware.
Processor Configuration Registers 2.21.5 GSTS_REG—Global Status Register This register reports general remapping hardware status. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 31 30 29 28 RO-V RO-V RO RO Reset Value 0b 0b 0b 0b RST/ PWR Description Uncore Translation Enable Status (TES) This field indicates the status of DMA-remapping hardware.
Processor Configuration Registers 2.21.6 RTADDR_REG—Root-Entry Table Address Register This register provides the base address of root-entry table.
Processor Configuration Registers 2.21.7 CCMD_REG—Context Command Register This register manages context cache. The act of writing the uppermost byte of the CCMD_REG with the ICC field set causes the hardware to perform the context-cache invalidation.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Access 0/0/0/VC0PREMAP 28–2Fh 0000000000000000h RW-V, RW, RO-V 64 bits 000000000h Reset Value RST/ PWR Description Uncore Context Actual Invalidation Granularity (CAIG) Hardware reports the granularity at which an invalidation request was processed through the CAIG field at the time of reporting invalidation completion (by clearing the ICC field).
Processor Configuration Registers 2.21.8 FSTS_REG—Fault Status Register This register indicates the various error status. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Access Reset Value 31:16 RO 0h RST/ PWR Description Reserved (RSVD) ROS-V 00h 7 RO 0h Reserved (RSVD) 0b Uncore Invalidation Time-out Error (ITE) Hardware detected a Device-IOTLB invalidation completion time-out.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 2 1 0 Datasheet, Volume 2 Access RO ROS-V RW1CS 0/0/0/VC0PREMAP 34–37h 00000000h RW1CS, ROS-V, RO 32 bits 00000h Reset Value 0b 0b 0b RST/ PWR Description Uncore Advanced Fault Overflow (AFO) Hardware sets this field to indicate advanced fault log overflow condition. At this time, a fault event is generated based on the programming of the Fault Event Control register.
Processor Configuration Registers 2.21.9 FECTL_REG—Fault Event Control Register This register specifies the fault event interrupt message control bits. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 31 326 Access RW 0/0/0/VC0PREMAP 38–3Bh 80000000h RW, RO-V 32 bits 00000000h Reset Value 1b 30 RO-V 0h 29:0 RO 0h RST/ PWR Description Uncore Interrupt Mask (IM) 0 = No masking of interrupt.
Processor Configuration Registers 2.21.10 FEDATA_REG—Fault Event Data Register This register specifies the interrupt message data. B/D/F/Type: Address Offset: Reset Value: Access: Size: Bit 2.21.11 Access 0/0/0/VC0PREMAP 3C–3Fh 00000000h RW 32 bits Reset Value RST/ PWR Description 31:16 RW 0000h Uncore Extended Interrupt Message Data (EIMD): This field is valid only for implementations supporting 32-bit interrupt data fields.
Processor Configuration Registers 2.21.13 AFLOG_REG—Advanced Fault Log Register This register specifies the base address of the memory-resident fault-log region. This register is treated as RsvdZ for implementations not supporting advanced translation fault logging (AFL field reported as 0 in the Capability register).
Processor Configuration Registers 2.21.14 PMEN_REG—Protected Memory Enable Register This register enables the DMA-protected memory regions setup through the PLMBASE, PLMLIMT, PHMBASE, PHMLIMIT registers. The register is always treated as RO for implementations not supporting protected memory regions (PLMR and PHMR fields reported as Clear in the Capability register). Protected memory regions may be used by software to securely initialize remapping structures in memory.
Processor Configuration Registers 2.21.15 PLMBASE_REG—Protected Low-Memory Base Register This register sets up the base address of DMA-protected low-memory region below 4 GB. This register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. This register is always treated as RO for implementations not supporting protected low memory region (PLMR field reported as Clear in the Capability register).
Processor Configuration Registers 2.21.16 PLMLIMIT_REG—Protected Low-Memory Limit Register This register sets up the limit address of DMA-protected low-memory region below 4 GB. This register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. This register is always treated as RO for implementations not supporting protected low memory region (PLMR field reported as Clear in the Capability register).
Processor Configuration Registers 2.21.17 PHMBASE_REG—Protected High-Memory Base Register This register sets up the base address of DMA-protected high-memory region. This register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. This register is always treated as RO for implementations not supporting protected high memory region (PHMR field reported as Clear in the Capability register).
Processor Configuration Registers 2.21.18 PHMLIMIT_REG—Protected High-Memory Limit Register This register sets up the limit address of DMA-protected high-memory region. This register must be set up before enabling protected memory through PMEN_REG, and must not be updated when protected memory regions are enabled. This register is always treated as RO for implementations not supporting protected high memory region (PHMR field reported as Clear in the Capability register).
Processor Configuration Registers 2.21.19 IQH_REG—Invalidation Queue Head Register This register indicates the invalidation queue head. This register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.21.
Processor Configuration Registers 2.21.21 IQA_REG—Invalidation Queue Address Register This register configures the base address and size of the invalidation queue. This register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register.
Processor Configuration Registers 2.21.22 ICS_REG—Invalidation Completion Status Register This register reports completion status of invalidation wait descriptor with Interrupt Flag (IF) set. This register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit 2.21.24 Access 0/0/0/VC0PREMAP A0–A3h 80000000h RW-L, RO-V 32 bits 00000000h Reset Value 30 RO-V 0b 29:0 RO 0h RST/ PWR Description Uncore Interrupt Pending (IP) Hardware sets the IP field whenever it detects an interrupt condition.
Processor Configuration Registers 2.21.25 IEADDR_REG—Invalidation Event Address Register This register specifies the Invalidation Event Interrupt message address. This register is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in the Extended Capability register. B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default 2.21.
Processor Configuration Registers 2.21.27 IRTA_REG—Interrupt Remapping Table Address Register This register provides the base address of Interrupt remapping table. This register is treated as RsvdZ by implementations reporting Interrupt Remapping (IR) as not supported in the Extended Capability register.
Processor Configuration Registers 2.21.28 IVA_REG—Invalidate Address Register This register provides the DMA address whose corresponding IOTLB entry needs to be invalidated through the corresponding IOTLB Invalidate register. This register is a write-only register.
Processor Configuration Registers 2.21.29 IOTLB_REG—IOTLB Invalidate Register This register invalidates IOTLB. The act of writing the upper byte of the IOTLB_REG with IVT field set causes the hardware to perform the IOTLB invalidation.
Processor Configuration Registers B/D/F/Type: Address Offset: Reset Value: Access: Size: BIOS Optimal Default Bit Access 0/0/0/VC0PREMAP 108–10Fh 0000000000000000h RW, RW-V, RO-V 64 bits 0000000000000h Reset Value RST/ PWR Description Uncore IOTLB Actual Invalidation Granularity (IAIG) Hardware reports the granularity at which an invalidation request was processed through this field when reporting invalidation completion (by clearing the IVT field). The following are the encodings for this field.