Guide

System Memory Design Guidelines (DDR-SDRAM)
R
Intel
®
852GM Chipset Platform Design Guide 93
Table 35. Data Signal Group Routing Guidelines
Parameter Definition
Signal Group SDQ[64:0], SDQS[7:0], SDM[7:0]
Motherboard Topology Daisy Chain with Parallel Termination
Reference Plane Ground Referenced
Characteristic Trace Impedance (Zo) 55 Ω ± 15%
Nominal Trace Width
Inner layers: 4 mils
Outer layers: 5 mils
Minimum Spacing to Trace Width Ratio
SDQ/SDM: 2 to 1 (e.g. 8 mil space to 4 mil trace)
SDQS: 3 to 1 (e.g. 12 mil space to 4 mil space)
Minimum Isolation Spacing to non-DDR Signals 20 mils
Package Length P1
700 mils ± 300 mils
(See package length Table 37 for exact lengths.)
Trace Length L1 – GMCH Signal Ball to Series
Termination Resistor Pad
Min = 0.5”
Max = 3.75”
Trace Length L2 – Series Termination Resistor Pad to
First SO-DIMM Pad
Max = 0.75”
Trace Length L3 – First SO-DIMM Pad to Last SO-
DIMM Pad
Min = 0.25”
Max = 1.0”
Trace Length L4 – Last SO-DIMM Pad to Parallel
Termination Resistor Pad
Max = 1.0”
Length Matching Requirements
SDQS to SCK/SCK#
See length matching Section
7.3.4.2
SDQ/SDM to SDQS, to ± 25mils, within each byte lane
See length matching Section
7.3.4.3 and Figure 4
NOTES:
1. Power distribution vias from Rt to Vtt are not included in this count.
2. The overall minimum and maximum length to the SO-DIMM must comply with clock length matching
requirements.
3. It is possible to route using 4 vias if trace segments L2 and L4 are routed on the same external layer as the
associated SO-DIMM, for example if L2 is on the same layer as SO-DIMM0.