8XC196Lx Supplement to 8XC196Kx, 8XC196Jx, 87C196CA User’s Manual August 2004 Order Number: 272973-003
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CONTENTS CHAPTER 1 GUIDE TO THIS MANUAL 1.1 MANUAL CONTENTS ................................................................................................... 1-1 1.2 RELATED DOCUMENTS .............................................................................................. 1-2 CHAPTER 2 ARCHITECTURAL OVERVIEW 2.1 MICROCONTROLLER FEATURES .............................................................................. 2-1 2.2 BLOCK DIAGRAM................................................................
8XC196LX SUPPLEMENT CHAPTER 6 SYNCHRONOUS SERIAL I/O PORT 6.1 SSIO 0 CLOCK REGISTER........................................................................................... 6-1 6.2 SSIO 1 CLOCK REGISTER........................................................................................... 6-2 CHAPTER 7 EVENT PROCESSOR ARRAY 7.1 EPA FUNCTIONAL OVERVIEW ................................................................................... 7-1 7.1.1 EPA Mask Registers ......................................
CONTENTS 8.6 PROGRAMMING THE J1850 CONTROLLER ............................................................ 8-16 8.6.1 Programming the J1850 Command (J_CMD) Register ..........................................8-16 8.6.2 Programming the J1850 Configuration (J_CFG) Register ......................................8-18 8.6.3 Programming the J1850 Delay Compensation (J_DLY) Register ...........................8-19 8.6.4 Programming the J1850 Status (J_STAT) Register ................................................
8XC196LX SUPPLEMENT FIGURES Figure 2-1 2-2 2-3 2-4 2-5 3-1 4-1 4-2 4-3 4-4 4-5 4-6 5-1 5-2 6-1 6-2 7-1 7-2 7-3 7-4 7-5 7-6 7-7 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-13 8-12 8-15 8-14 8-16 8-17 8-18 8-19 9-1 10-1 vi Page 8XC196Lx Block Diagram ............................................................................................2-2 Clock Circuitry (87C196LA, LB Only) ...........................................................................
CONTENTS FIGURES Figure 11-1 11-2 A-1 A-2 A-3 Page Slave Programming Circuit.........................................................................................11-3 Serial Port Programming Circuit .................................................................................11-4 87C196LA 52-pin PLCC Package ............................................................................... A-3 87C196LB 52-pin PLCC Package ...............................................................................
XC196LX SUPPLEMENT TABLES Table 1-1 2-1 2-2 2-3 2-4 3-1 3-2 3-3 3-4 4-1 5-1 7-1 7-2 8-1 8-2 8-3 8-4 11-1 11-2 11-3 11-4 A-1 A-2 A-3 A-4 A-5 A-6 viii Page Related Documents ......................................................................................................1-2 Features of the 8XC196Lx and 8XC196Kx Product Famiies .......................................2-1 State Times at Various Frequencies ............................................................................
1 Guide to This Manual
CHAPTER 1 GUIDE TO THIS MANUAL This document is a supplement to the 8XC196Kx, 8XC196Jx, 87C196CA Microcontroller Family User’s Manual. It describes the differences between the 8XC196Lx and the 8XC196Kx family of microcontrollers. For information not found in this supplement, please consult the 8XC196Kx, 8XC196Jx, 87C196CA Microcontroller Family User’s Manual (order number 272258) or the 8XC196Lx datasheets listed in the “Related Documents” section of this chapter. 1.
8XC196LX SUPPLEMENT Appendix A — Signal Descriptions — provides reference information for the 8XC196Lx device pins, including descriptions of the pin functions, reset status of the I/O and control pins, and package pin assignments. Glossary — defines terms with special meaning used throughout this supplement. Index — lists key topics with page number references. 1.
2 Architectural Overview
CHAPTER 2 ARCHITECTURAL OVERVIEW This chapter describes architectural differences between the 8XC196Lx (87C196LA, 87C196LB, and 83C196LD) and the 8XC196Kx (8XC196Kx, 8XC196Jx, and 87C196CA) microcontroller families. Both the 8XC196Lx and the 8XC196Kx are designed for high-speed calculations and fast I/O, and share a common architecture and instruction set with few deviations. This chapter provides a high-level overview of the deviations between the two families.
8XC196LX SUPPLEMENT 2.2 BLOCK DIAGRAM Figure 2-1 is a simplified block diagram that shows the major blocks within the microcontroller. Observe that the slave port peripheral does not exist on the 8XC196Lx. I/O Core (CPU, Memory Controller) Optional ROM/ OTPROM Interrupt Controller Clock and Power Mgmt. Optional Code/Data RAM Peripheral Transaction Server SIO SSIO EPA A/D WDT J1850 Note: The J1850 peripheral is unique to the 87C196LB device.
ARCHITECTURAL OVERVIEW Disable PLL (Powerdown) Filter FXTAL1 XTAL2 Disable Oscillator (Powerdown) 2FXTAL1 Phase-locked Oscillator FXTAL1 XTAL1 Phase Comparator PLLEN Phase-locked Loop Clock Multiplier 1 0 f Disable Clock Input (Powerdown) Divide by two Circuit To reset logic f/2 Disable Clocks (Idle, Powerdown) Clock Generators Clock Failure Detection CPU Clocks (PH1, PH2) Peripheral Clocks (PH1, PH2) f/2 Programmable Divider (CLK1:0) OSC 0 CLKOUT 1 Disable Clocks (Powerdown) A5290-01
8XC196LX SUPPLEMENT XTAL1 t t 1 State Time 1 State Time PH1 PH2 CLKOUT Phase 1 Phase 2 Phase 1 Phase 2 A0805-01 Figure 2-3. Internal Clock Phases (Assumes PLL is Bypassed) The combined period of phase 1 and phase 2 of the internal CLKOUT signal defines the basic time unit known as a state time or state. Table 2-2 lists state time durations at various frequencies. Table 2-2.
ARCHITECTURAL OVERVIEW TXHCH XTAL1 (16 MHz) f PLLEN = 0 t = 62.5ns Internal CLKOUT f PLLEN = 1 t = 31.25ns Internal CLKOUT A3376-01 Figure 2-4. Effect of Clock Mode on Internal CLKOUT Frequency Table 2-3. Relationships Between Input Frequency, Clock Multiplier, and State Times FXTAL1 (Frequency on XTAL1) PLLEN Multiplier f (Input Frequency to the Divide-by-two Circuit) t (Clock Period) State Time 4 MHz 0 1 4 MHz 250 ns 500 ns 8 MHz 0 1 8 MHz 125 ns 250 ns 12 MHz 0 1 12 MHz 83.
8XC196LX SUPPLEMENT Address: Reset State: USFR1 (read only) 1FF2H XXH The UPROM special-function register 1 (USFR1) reflects the status of unerasable, programmable read-only memory (UPROM) locations. This read-only register reflects the status of two bits that control the output frequency on CLKOUT. 7 0 — — — Bit Number Bit Mnemonic — — — CLK1 CLK0 Function 7:2 — Reserved.
ARCHITECTURAL OVERVIEW 2.5.1 I/O Ports The I/O ports of the 8XC196Lx are functionally identical to those of the 8XC196Jx. However, on the 87C196LA and LB the reset state level of all 41 general-purpose I/O pins has changed from a weak logic “1” (wk1) to a weak logic “0” (wk0). 2.5.
3 Address Space
CHAPTER 3 ADDRESS SPACE This chapter describes the differences in the address space of the 8XC196Lx from that of the 8XC196Kx. 3.1 ADDRESS PARTITIONS Table 3-1 is an address map of the 8XC196Lx and 8XC196Kx microcontroller family members. Table 3-1.
8XC196LX SUPPLEMENT Table 3-1.
ADDRESS SPACE Address 03FFH (CA, JT, JV, KT) General-purpose Register RAM 02FFH (LA, LB) 01FFH (JR, KR) 017FH (LD) 0100H 00FFH Address 03FFH 0100H 00FFH 0000H General-purpose Register RAM Upper Register File Stack Pointer Lower Register File CPU SFRs 001AH 0019H 0018H 0017H 0000H A5260-01 Figure 3-1. Register File Address Map Table 3-2.
8XC196LX SUPPLEMENT 3.3 PERIPHERAL SPECIAL-FUNCTION REGISTERS Table 3-3 lists the peripheral SFR addresses. Highlighted addresses are unique to the 8XC196Lx. Table 3-3.
ADDRESS SPACE Table 3-3.
8XC196LX SUPPLEMENT 3.4 WINDOWING Windowing maps a segment of higher memory (the upper register file or peripheral SFRs) into the lower register file. The window selection register (WSR) selects a 32-, 64- or 128-byte segment of higher memory to be windowed into the top of the lower register file space. Table 3-4 lists the WSR values for windowing the upper register file for both the 8XC196Lx and 8XC196Kx. Table 3-4.
ADDRESS SPACE Table 3-4.
8XC196LX SUPPLEMENT Table 3-4. Windows (Continued) Base Address WSR Value for 32-byte Window (00E0–00FFH) WSR Value for 64-byte Window (00C0–00FFH) WSR Value for 128-byte Window (0080–00FFH) Upper Register File (CA, JR, JT, JV, KR, KT, LA, LB, LD) 0160H 4BH 0140H 4AH 0120H 49H 0100H 48H NOTE: 3-8 25H 24H 12H Locations 1FE0–1FFFH contain memory-mapped SFRs that cannot be accessed through a window.
4 Standard and PTS Interrupts
CHAPTER 4 STANDARD AND PTS INTERRUPTS The interrupt structure of the 8XC196Lx is the same as that of the 8XC196Jx. The only difference is that the slave port interrupts (INT08:06) now support the J1850 controller peripheral. 4.1 INTERRUPT SOURCES, VECTORS, AND PRIORITIES Table 4-1 lists the 8XC196Lx’s interrupts sources, default priorities (30 is highest and 0 is lowest), and vector addresses.
8XC196LX SUPPLEMENT Table 4-1.
STANDARD AND PTS INTERRUPTS 4.2.1 Interrupt Mask Registers Figures 4-1 and 4-2 illustrate the interrupt mask registers for the 8XC196Lx microcontrollers. Address: Reset State: INT_MASK 0008H 00H The interrupt mask (INT_MASK) register enables or disables (masks) individual interrupt requests. (The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK is the low byte of the processor status word (PSW).
8XC196LX SUPPLEMENT Address: Reset State: INT_MASK1 0013H 00H The interrupt mask 1 (INT_MASK1) register enables or disables (masks) individual interrupt requests. (The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK1 can be read from or written to as a byte register. PUSHA saves this register on the stack and POPA restores it.
STANDARD AND PTS INTERRUPTS Address: Reset State: INT_PEND 0009H 00H When hardware detects an interrupt request, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit. Software can generate an interrupt by setting the corresponding interrupt pending bit.
8XC196LX SUPPLEMENT Address: Reset State: INT_PEND1 0012H 00H When hardware detects an interrupt request, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit. Software can generate an interrupt by setting the corresponding interrupt pending bit.
STANDARD AND PTS INTERRUPTS Address: Reset State: PTSSEL 0004H 0000H The PTS select (PTSSEL) register selects either a PTS microcode routine or a standard interrupt service routine for each interrupt request. Setting a bit selects a PTS microcode routine; clearing a bit selects a standard interrupt service routine. In PTS modes that use the PTSCOUNT register, hardware clears the corresponding PTSSEL bit when PTSCOUNT reaches zero.
8XC196LX SUPPLEMENT Address: Reset State: PTSSRV 0006H 0000H The PTS service (PTSSRV) register is used by the hardware to indicate that the final PTS interrupt has been serviced by the PTS routine. When PTSCOUNT reaches zero, hardware clears the corresponding PTSSEL bit and sets the PTSSRV bit, which requests the end-of-PTS interrupt. When the end-of-PTS interrupt is called, hardware clears the PTSSRV bit. The end-of-PTS interrupt service routine must set the PTSSEL bit to re-enable the PTS channel.
5 I/O Ports
CHAPTER 5 I/O PORTS The I/O ports of the 8XC196Lx are functionally identical to those of the 8XC196Jx. However, on the 87C196LA and LB, the reset state level of all 41 general-purpose I/O pins has changed from a weak logic “1” (wk1) to a weak logic “0” (wk0). This chapter outlines the differences between the 87C196LA, LB and the 8XC196Kx controllers. 5.1 I/O PORTS OVERVIEW Table 5-1 provides an overview of the 8XC196Lx and 8XC196Kx I/O ports. Table 5-1.
8XC196LX SUPPLEMENT input signals set SFDIR. Even if a pin is to be used in special-function mode, you must still initialize the pin as an input or output by writing to the port direction register. Resistor R1 provides ESD protection for the pin. Input signals are buffered. The standard ports use Schmitt-triggered buffers for improved noise immunity. Port 5 uses a standard input buffer because of the high speeds required for bus control functions.
I/O PORTS Internal Bus VCC Px_REG 0 SFDATA 1 Q1 I/O Pin Px_DRV 0 SFDIR 1 Q2 RESET# VSS Px_MODE Sample Latch Px_PIN Q 150Ω to 200Ω R1 Buffer D LE Read Port PH1 Clock Medium Pullup 300ns Delay Q3 RESET# VSS RESET# Weak Pullup R Q Any Write to Px_MODE Q4 S VSS A5265-01 Figure 5-1. Ports 1, 2, 5, and 6 Internal Structure (87C196LA, LB Only) 5.2.
8XC196LX SUPPLEMENT impedance input, or open-drain output. The port direction and data output registers select the configuration for each pin. Complementary output means that the microcontroller drives the signal high or low. High-impedance input means that the microcontroller floats the signal. Open-drain output means that the microcontroller drives the signal low or floats it.
I/O PORTS in using this pin. Be certain that your system meets the VIH specifications during reset to prevent inadvertent entry into ONCE mode or a test mode. 3. 5.3 Following reset, P2.7/CLKOUT carries the strongly driven CLKOUT signal. It is not held low. When P2.7/CLKOUT is configured as CLKOUT, it is always a complementary output. INTERNAL STRUCTURE FOR PORTS 3 AND 4 (ADDRESS/DATA BUS) Figure 5-2 shows the logic of ports 3 and 4.
8XC196LX SUPPLEMENT Internal Bus VCC Px_REG 1 Address/Data 0 Q1 Bus Control Select 0 = Address/Data 1 = I/O I/O Pin Q2 P34_DRV RESET# 150Ω to 200Ω Sample Latch Px_PIN Q VSS R1 Buffer D LE Read Port PH1 Clock Medium Pullup 300ns Delay Q3 RESET# VSS Weak Pullup Q4 VSS A5264-01 Figure 5-2.
6 Synchronous Serial I/O Port
CHAPTER 6 SYNCHRONOUS SERIAL I/O PORT The synchronous serial I/O (SSIO) port on the 8XC196Lx has been enhanced, implementing two new special function registers (SSIO0_CLK and SSIO1_CLK) that allow you to select the operating mode and configure the phase and polarity of the serial clock signals. 6.1 SSIO 0 CLOCK REGISTER The SSIO 0 clock (SSIO_CLK) register selects the phase and polarity for the SC0 clock signal. In standard mode, SC0 is channel 0’s clock signal.
8XC196LX SUPPLEMENT For transmissions, SSIO0_CLK determines whether the SSIO shifts out data bits on rising or falling clock edges. For receptions, SSIO0_CLK determines whether the SSIO samples data bits on rising or falling clock edges. 6.2 SSIO 1 CLOCK REGISTER SSIO1_CLK selects the SSIO mode of operation (standard, duplex, or channel-select), enables the channel-select master contention interrupt request, and selects the phase and polarity for the serial clock (SC1) for channels.
SYNCHRONOUS SERIAL I/O PORT Address: SSIO1_CLK (Continued) Reset State: 1FB7H 00H The SSIO 1 clock (SSIO1_CLK) register selects the SSIO mode of operation (standard, duplex, or channel-select), enables the channel-select master contention interrupt request, and selects the phase and polarity for the serial clock (SC1) for channel 1.
7 Event Processor Array
CHAPTER 7 EVENT PROCESSOR ARRAY The EPA on the 8XC196Lx is functionally identical to that of the 8XC196Jx; however, the 8XC196Lx has only two capture/compare channels without pins instead of four. In addition, the 83C196LD has no compare-only channels. 7.1 EPA FUNCTIONAL OVERVIEW Table 7-1 lists the capture/compare (with and without pins) and compare-only channels for each device in the 8XC196Lx and 8XC196Kx families. Table 7-1.
8XC196LX SUPPLEMENT Timer-Counter Unit TIMER1 TIMER2 EPA 3:0 Capture/Compare Channel 0–3 EPA 3:0 Interrupts Capture/Compare Channel 6–7 EPA8 / COMP0 Capture/Compare Channel 8 Compare-only Channel 0 EPA9 / COMP1 Indirect Interrupt Processor Logic EPAx Interrupt Capture/Compare Channel 9 Compare-only Channel 1 A5269-01 Figure 7-1.
EVENT PROCESSOR ARRAY Timer-Counter Unit TIMER1 TIMER2 EPA 3:0 Capture/Compare Channel 0–3 EPA 3:0 Interrupts Capture/Compare Channel 6–7 EPA8 Capture/Compare Channel 8 Indirect Interrupt Processor Logic EPA9 EPAx Interrupt Capture/Compare Channel 9 A5281-01 Figure 7-2.
8XC196LX SUPPLEMENT 7.1.1 EPA Mask Registers Figures 7-3 and 7-4 illustrate the EPA mask registers, EPA_MASK and EPA_MASK1, for the 8XC196Lx microcontroller family. Address: Reset State: EPA_MASK 1FA0H 0000H The EPA interrupt mask (EPA_MASK) register enables or disables (masks) interrupts associated with the shared EPAx interrupt.
EVENT PROCESSOR ARRAY 7.1.2 EPA Pending Registers Figures 7-5 and 7-6 illustrate the EPA pending registers, EPA_PEND and EPA_PEND1, for the 8XC196Lx microcontroller family. Address: Reset State: EPA_PEND 1FA2H 0000H When hardware detects a pending EPA6–9 or OVR0–3, 8–9 interrupt request, it sets the corresponding bit in the EPA interrupt pending register (EPA_PEND or EPA_PEND1). The EPAIPV register contains a number that identifies the highest priority, active, shared interrupt source.
8XC196LX SUPPLEMENT 7.1.3 EPA Interrupt Priority Vector Register Figure 7-7 illustrates the EPA interrupt priority vector (EPAIPV) register for the 8XC196Lx microcontroller family. Address: Reset State: EPAIPV 1FA8H 00H When an EPAx interrupt occurs, the EPA interrupt priority vector (EPAIPV) register contains a number that identifies the highest priority, active, multiplexed interrupt source (see Table 7-2).
8 J1850 Communications Controller
CHAPTER 8 J1850 COMMUNICATIONS CONTROLLER The J1850 communications controller manages communications between multiple network nodes. This integrated peripheral supports the 10.4 Kb/s VPW (variable pulse width) mediumspeed class B in-vehicle network protocol. It also supports both the standard and in-frame response (IFR) message framing as specified by the Society of Automotive Engineering (SAE) J1850 (revised May 1994) technical standards.
8XC196LX SUPPLEMENT The J1850 controller can handle network protocol functions including message frame sequencing, bit arbitration, in-frame response (IFR) messaging, error detection, and delay compensation. The J1850 communications controller (Figure 8-2) consists of a control state machine (CSM), symbol synchronization and timing (SST) circuitry, six control and status registers, transmit and receive buffers, and an interrupt handler.
J1850 COMMUNICATIONS CONTROLLER 8.2 J1850 CONTROLLER SIGNALS AND REGISTERS Table 8-1 describes the J1850 controller’s pins, and Table 8-2 describes the control and status registers. Table 8-1. J1850 Controller Signals Signal Type RXJ1850 I Description Receive Carries digital symbols from a remote transceiver to the J1850 controller. TXJ1850 O Transmit Carries digital symbols from the J1850 controller to a remote transceiver. Table 8-2.
8XC196LX SUPPLEMENT Table 8-2. Control and Status Registers (Continued) Mnemonic INT_MASK Address 0008H Description Interrupt Mask Bits 6 and 7 in this register enable and disable the J1850 receive and transmit interrupt requests, respectively. INT_MASK1 0013H Interrupt Mask 1 Bit 0 in this register enables and disables the J1850 bus error interrupt request.
J1850 COMMUNICATIONS CONTROLLER 8.3.1.2 Bus Contention Bus contention arises when multiple nodes attempt to access and transmit message frames across the J1850 bus simultaneously. This creates a conflict on the bus. The recognition of conflicting symbols or bits on the bus is referred to as contention detection.
8XC196LX SUPPLEMENT 8.3.2.1 Clock Prescaler Because the 87C196LB microcontroller can operate at a variety of input frequencies (FXTAL1), the clock prescaler circuitry is used to provide a single, internal clock frequency (f/2) to ensure that the J1850 peripheral is clocked at the proper operating frequency. This is accomplished through the programmable clock prescaler bits, PRE1:0 in the J_CFG register (Figure 8-17 on page 8-18).
J1850 COMMUNICATIONS CONTROLLER 1 0 1 128µS or "passive 1" 1 0 0 1 64µS or "passive 0" 0 64µS "active 1" 128µS "active 0" A5219-01 Figure 8-3. Huntzicker Symbol Definition for J1850 A symbol is defined as a timing-level formatted bit. The VPW symbol timing requirements stipulate that there is one symbol per transition and one transition per symbol. This ensures that a message frame will always result in a uniform square waveform of varying level durations.
8XC196LX SUPPLEMENT of arbitration, nodes A, C, and D are all transmitting an “active 0” symbol, thus the idle state of the “passive 1” symbol is overruled in favor of the driven state of the “active 0” symbol. Node C is the next node to discontinue transmitting when it attempts to take control of the bus by transmitting an “active 1” symbol. However, nodes A and D maintain control by continuing to drive the bus with an “active 0” symbol.
J1850 COMMUNICATIONS CONTROLLER Standard Frame S O F 1-3 Bytes Header 1-11 Bytes Data† 1 Byte CRC E E I O O F D F S 1 Byte CRC E N O B D In-frame Response (IFR) Frame S O F † 1-3 Bytes Header 1-11 Bytes Data† 1-32 Bytes IFR Data 0-1 Byte CRC E E I O O F D F S The number of data bytes to be transferred is unspecified if 0EH is written to J_CMD3:0. A5225-01 Figure 8-6.
8XC196LX SUPPLEMENT (J_CFG.7) and considers whether the IFR message response has a CRC byte appended. Figure 8-7 depicts the SAE preferred, active-level state bit format timing for the NB. 1 64µS 1 or 0 128µS 0 NB for IFR without CRC NB for IFR with CRC A5220-01 Figure 8-7. Huntzicker Symbol Definition for the Normalization Bit 8.4.1.
J1850 COMMUNICATIONS CONTROLLER 200µS 1 0 "Start of Frame (SOF)" 1 200µS 0 "End of Data (EOD)" 1 280µS 0 "End of Frame (EOF)" 1 300µS+ 0 "In-frame Separation (IFS)" 768µS+ 1 "Break Signal (BRK)" 0 A5221-01 Figure 8-8. Definition for Start and End of Frame Symbols Table 8-4 details the symbol timing characteristics supported by the 87C196LB. Table 8-4.
8XC196LX SUPPLEMENT 8.4.2 In-frame Response Messaging There are three types of in-frame response (IFR) message framings: type 1 (a single byte from a single responder), type 2 (a single byte from multiple responders), and type 3 (multiple bytes from a single responder). Like the standard message frame, the IFR frame is composed of header, data, and CRC bytes, and a series of start and end symbols.
J1850 COMMUNICATIONS CONTROLLER IFR Data Field†† In-frame Response (IFR) Frame S O F 1-3 Bytes Header 1-11 Bytes Data† 1 Byte CRC E 0-1 Byte N D D .......... D O 31 CRC B 0 1 D E E I O O F D F S † The number of data bytes to be transferred is unspecified if 0EH is written to J_CMD3:0. †† Each D block in the IFR data field represents a byte of data from a different remote node. X A5227-01 Figure 8-10. IFR Type 2 Message Frame 8.4.2.
8XC196LX SUPPLEMENT Address: Reset State: J_TX 1F50H 00H The J1850 transmitter (J_TX) register transfers data in byte increments to the J1850 bus from the microcontroller CPU. This register is buffered to allow for transmission of a second data byte while the first data byte is being shifted out. This byte register can be read or written, and is addressable through windowing.
J1850 COMMUNICATIONS CONTROLLER NOTE An overrun condition can occur on transmission if the transmit buffer, JTX_BUF, is overwritten. 8.5.2 Receiving Messages For a message reception, after a SOF is detected on the bus, the controller starts to shift data symbols into the J1850 receive buffer (JRX_BUF) until an entire data byte has been received. This byte is automatically transferred into the J1850 receive (J_RX) register (Figure 8-14) and the subsequent byte is written into the empty JRX_BUF.
8XC196LX SUPPLEMENT If a third byte is received before J_RX is read, a J1850ST core interrupt is generated and the OVR_UNDR (J_STAT.3) bit records a receiver overrun error in the J_STAT register. 8.5.3 IFR Messages In-frame response (IFR) messaging is identical in setup to standard messaging for both transmission and reception. It uses the same registers to configure, communicate, and control data.
J1850 COMMUNICATIONS CONTROLLER Address: Reset State: J_CMD 1F51H 00H The J1850 command (J_CMD) register determines the messaging type, specifies the number of bytes to be transmitted in the next message frame, and updates the status of the message transmission in progress. This byte register can be directly addressed through windowing. You must write to this register prior to transmitting every message.
8XC196LX SUPPLEMENT 8.6.2 Programming the J1850 Configuration (J_CFG) Register The J1850 configuration register (Figure 8-17) selects the proper oscillator prescaler, initiates a transmission break for debugging, invokes clock quadrupling operation, and selects the normalization bit format.
J1850 COMMUNICATIONS CONTROLLER Address: Reset State: J_CFG 1F54H 00H The J1850 configuration (J_CFG) register selects the proper oscilator prescaler, initiates transmission break for debug, invokes clock quadrupling operation, and selects the normalizartion bit format. This byte register can be directly addressed through windowing. All J1850 bus activity is ignored until you first write to this register.
8XC196LX SUPPLEMENT Address: Reset State: J_DLY 1F58H 00H The J1850 delay (J_DLY) register allows you compensate for the inherent propagation delays and to accurately resolve bus contention during arbitration. This byte register can be directly addressed through windowing. 7 0 — — Bit Number Bit Mnemonic 7:5 — 4:0 DLY4:0 — DLY4 DLY3 DLY2 DLY1 DLY0 Function Reserved; for compatibility with future devices, write zeros to these bits.
J1850 COMMUNICATIONS CONTROLLER 8.6.4 Programming the J1850 Status (J_STAT) Register The J1850 status register (Figure 8-19) provides the current status of the message and the four interrupt sources associated with the J1850 protocol. Address: Reset State: J_STAT 1F53H 00H The J1850 status (J_STAT) register provides the current status of the message transfer, the receive and transmit buffers, and the four interrupt sources associated with the J1850 protocol.
8XC196LX SUPPLEMENT Address: Reset State: J_STAT 1F53H 00H The J1850 status (J_STAT) register provides the current status of the message transfer, the receive and transmit buffers, and the four interrupt sources associated with the J1850 protocol. This byte register can be directly addressed through windowing. You must write to this register before transmitting each message. Reading this register clears all bits except BUS_STAT.
9 Minimum Hardware Considerations
CHAPTER 9 MINIMUM HARDWARE CONSIDERATIONS This chapter discusses the major hardware consideration differences between the 8XC196Lx and the 8XC196Kx. The 8XC196Lx has implemented a reset source SFR that reveals the source of the most recent reset request. 9.1 IDENTIFYING THE RESET SOURCE The reset source (RSTSRC) register indicates the source of the last reset that the microcontroller encountered (Figure 9-1). If more than one reset occurs at the same time, all of the corresponding RSTSRC bits are set.
8XC196LX SUPPLEMENT 9.2 DESIGN CONSIDERATIONS FOR 8XC196LA, LB, AND LD With the exception of a few new multiplexed functions, the 8XC196Lx microcontrollers are pin compatible with the 8XC196Jx microcontrollers. The 8XC196Jx microcontrollers are 52-lead versions of 8XC196Kx microcontrollers. Follow these recommendations to help maintain hardware and software compatibility between the 8XC196Lx, 8XC196Kx, and future microcontrollers. • Bus width.
10 Special Operating Modes
CHAPTER 10 SPECIAL OPERATING MODES The 8XC196Lx’s idle and powerdown modes are the same as those of the 8XC196Kx. However, the clock circuitry has changed, and the on-circuit emulation (ONCE) special-purpose mode operation has changed slightly because of the new reset state pin levels that have been implemented. 10.
8XC196LX SUPPLEMENT Disable PLL (Powerdown) Filter FXTAL1 XTAL2 Disable Oscillator (Powerdown) 2FXTAL1 Phase-locked Oscillator FXTAL1 XTAL1 Phase Comparator Phase-locked Loop Clock Multiplier PLLEN 1 0 f Disable Clock Input (Powerdown) Divide by two Circuit To reset logic f/2 Disable Clocks (Idle, Powerdown) Clock Generators Clock Failure Detection CPU Clocks (PH1, PH2) Peripheral Clocks (PH1, PH2) f/2 Programmable Divider (CLK1:0) OSC 0 CLKOUT 1 Disable Clocks (Powerdown) A5290-01 Fig
SPECIAL OPERATING MODES an output. If you choose to configure this pin as an input, always hold it low during reset and ensure that your system meets the VIH specification to prevent inadvertent entry into ONCE mode.
11 Programming the Nonvolatile Memory
CHAPTER 11 PROGRAMMING THE NONVOLATILE MEMORY The 87C196LA and LB microcontrollers contain 24 Kbytes (2000–7FFFH) of one-time-programmable read-only memory (OTPROM). OTPROM is similar to EPROM, but it comes in a windowless package and cannot be erased. You have the option of programming the OTPROM yourself or having the factory program it as a quick-turn ROM product (the latter option may not be available for all devices).
8XC196LX SUPPLEMENT Table 11-2.
PROGRAMMING THE NONVOLATILE MEMORY CLOCK VCC XTAL1 VCC RESET# VCC RESET# 0.1 µF 10kΩ VSS P4.7:0 P3.7:0 EA# VPP PBUS Pullups Required P4.7 - P3.0 EA# P2.6 CPVER VPP P2.4 AINC# P2.2 PROG# P2.1 PALE# P2.0 PVER VCC VREF P0.7/PMODE.3 P0.6/PMODE.2 P0.5/PMODE.1 P0.4/PMODE.0 ANGND 87C196LA, LB A5277-01 Figure 11-1. Slave Programming Circuit Table 11-3.
8XC196LX SUPPLEMENT 11.4 SERIAL PORT PROGRAMMING CIRCUIT AND ADDRESS MAP Figure 11-2 shows the circuit and Table 11-4 details the address map for serial port programming. 30 pF 30 pF XTAL1 XTAL2 VCC RESET# 10 µF VREF P0.7/PMODE.3 P0.6/PMODE.2 P0.5/PMODE.1 P0.4/PMODE.0 ANGND VCC VPP VCC A EA# B C P2.1/RXD VPP P2.0/TXD 0.01 µF 87C196LA, LB RXD VCC 2N2222A 1.8kΩ 1.8kΩ 1N914 RXD 2N2907 TXD TXD 1.8kΩ 1.8kΩ 1N914 5 9 4 8 3 7 2 6 1 1.8kΩ 10µF A5278-01 Figure 11-2.
PROGRAMMING THE NONVOLATILE MEMORY Table 11-4.
A Signal Descriptions
APPENDIX A SIGNAL DESCRIPTIONS This appendix provides reference information for the pin functions of the 8XC196Lx microcontrollers. A.1 FUNCTIONAL GROUPINGS OF SIGNALS Tables A-1, A-2, and A-3 list the signal assignments for the 8XC196Lx microcontrollers, grouped by function. A diagram of each microcontroller shows the pin location of each signal.
8XC196LX SUPPLEMENT Table A-1. 87C196LA Signals Arranged by Functional Categories Addr & Data Name Input/Output (Cont’d) Pin Name Program Control Pin Name Processor Control Pin Name Pin AD0 22 P2.1 / RXD 28 AINC# 30 EA# 24 AD1 21 P2.2 29 CPVER 31 EXTINT 29 AD2 20 P2.4 30 PACT# 32 PLLEN 6 AD3 19 P2.6 31 PALE# 28 RESET# 23 AD4 18 P2.7 32 PBUS.0 22 XTAL1 52 AD5 17 P3.0 22 PBUS.1 21 XTAL2 51 AD6 16 P3.1 21 PBUS.2 20 AD7 15 P3.2 20 PBUS.
7 6 5 4 3 2 1 52 51 50 49 48 47 AD15 / P4.7 / PBUS.15 P5.2 / PLLEN / WR# / WRL# P5.3 / RD# VPP VSS P5.0 / ADV# / ALE VSS1 XTAL1 XTAL2 P6.7 / SD1 P6.6 / SC1 P6.5 / SD0 P6.4 / SC0 SIGNAL DESCRIPTIONS 8 9 10 11 12 13 14 15 16 17 18 19 20 xx87C196LA20 View of component as mounted on PC board 46 45 44 43 42 41 40 39 38 37 36 35 34 P6.1 / EPA9 / COMP1 P6.0 / EPA8 / COMP0 P1.0 / EPA0 / T2CLK P1.1 / EPA1 P1.2 / EPA2 / T2DIR P1.3 / EPA3 VREF ANGND P0.7 / ACH7 / PMODE.3 P0.6 / ACH6 / PMODE.2 P0.
8XC196LX SUPPLEMENT Table A-2. 87C196LB Signals Arranged by Functional Categories Addr & Data Name Input/Output (Cont’d) Pin Name Program Control Pin Name Processor Control Pin Name Pin AD0 22 P2.1 / RXD 28 AINC# 30 EA# 24 AD1 21 P2.2 29 CPVER 31 EXTINT 29 AD2 20 P2.4 / RXJ1850 30 PACT# 32 PLLEN 6 AD3 19 P2.6 / TXJ1850 31 PALE# 28 RESET# 23 AD4 18 P2.7 32 PBUS.0 22 XTAL1 52 AD5 17 P3.0 22 PBUS.1 21 XTAL2 51 AD6 16 P3.1 21 PBUS.
7 6 5 4 3 2 1 52 51 50 49 48 47 AD15 / P4.7 / PBUS.15 P5.2 / PLLEN /WR# / WRL# P5.3 / RD# VPP VSS (core) P5.0 / ADV# / ALE VSS1 (port) XTAL1 XTAL2 P6.7 / SD1 P6.6 / SC1 P6.5 / SD0 P6.4 / SC0 SIGNAL DESCRIPTIONS 8 9 10 11 12 13 14 15 16 17 18 19 20 xx87C196LB20 View of component as mounted on PC board 46 45 44 43 42 41 40 39 38 37 36 35 34 P6.1 / EPA9 / COMP1 P6.0 / EPA8 / COMP0 P1.0 / EPA0 / T2CLK P1.1 / EPA1 P1.2 / EPA2 / T2DIR P1.3 / EPA3 VREF ANGND P0.7 / ACH7 / PMODE.3 P0.6 / ACH6 / PMODE.2 P0.
8XC196LX SUPPLEMENT Table A-3. 83C196LD Signals Arranged by Functional Categories Addr & Data Input/Output Name Name Pin Input/Output (Cont’d) Pin Name Processor Control Pin Name Pin AD0 22 P1.0/EPA0/T2CLK 44 P4.7 7 CLKOUT 32 AD1 21 P1.1/EPA1 43 P5.0 2 EA# 24 AD2 20 P1.2/EPA2/T2DIR 42 P5.2 6 EXTINT 29 AD3 19 P1.3/EPA3 41 P5.3 5 ONCE# 31 AD4 18 P2.0/TXD 27 P6.0/EPA8 45 RESET# 23 AD5 17 P2.1/RXD 28 P6.1/EPA9 46 XTAL1 52 AD6 16 P2.2 29 P6.
7 6 5 4 3 2 1 52 51 50 49 48 47 AD15 / P4.7 P5.2 / WR# / WRL# P5.3 / RD# VPP VSS P5.0 / ADV# / ALE VSS XTAL1 XTAL2 P6.7 / SD1 P6.6 / SC1 P 6. 5 / S D0 P6.4 / SC0 SIGNAL DESCRIPTIONS 8 9 10 11 12 13 14 15 16 17 18 19 20 xx83C196LD View of component as mounted on PC board 46 45 44 43 42 41 40 39 38 37 36 35 34 P6.1 / EPA9 P6.0 / EPA8 P1.0 / EPA0 / T2CLK P1.1 / EPA1 P1.2 / EPA2 / T2DIR P1.3 / EPA3 VCC VSS P0.7 P0.6 P0.5 P0.4 P0.3 AD1 / P3.1 AD0 / P3.0 RESET# EA# VSS VCC P2.0 / TXD P2.1 / RXD P2.
8XC196LX SUPPLEMENT Table A-5. 87C196LA, LB Default Signal Conditions Port Signals Alternate Functions During RESET# Active Upon RESET# Inactive (Note 6) Idle Powerdown P0.7:2 ACH7:2 P1.0 EPA0/T2CLK P1.1 EPA1 WK0 WK0 (Note 1) (Note 1) P1.2 EPA2/T2DIR WK0 WK0 (Note 1) (Note 1) P1.3 EPA3 WK0 WK0 (Note 1) (Note 1) P2.0 TXD WK0 WK0 (Note 1) (Note 1) P2.1 RXD WK0 WK0 (Note 1) (Note 1) P2.2 EXTINT WK0 WK0 (Note 1) (Note 1) P2.
SIGNAL DESCRIPTIONS Table A-6. 83C196LD Default Signal Conditions Port Signals Alternate Functions During RESET# Active Upon RESET# Inactive (Note 6) Idle Powerdown P0.7:2 — P1.0 EPA0/T2CLK P1.1 EPA1 WK1 WK1 (Note 1) (Note 1) P1.2 EPA2/T2DIR WK1 WK1 (Note 1) (Note 1) P1.3 EPA3 WK1 WK1 (Note 1) (Note 1) P2.0 TXD WK1 WK1 (Note 1) (Note 1) P2.1 RXD WK1 WK1 (Note 1) (Note 1) P2.2 EXTINT WK1 WK1 (Note 1) (Note 1) P2.4 — WK1 WK1 (Note 1) (Note 1) P2.
Glossary
GLOSSARY This glossary defines acronyms, abbreviations, and terms that have special meaning in this manual. (Chapter 1 discusses notational conventions and general terminology.) absolute error The maximum difference between corresponding actual and ideal code transitions. Absolute error accounts for all deviations of an actual A/D converter from an ideal converter. accumulator A register or storage location that forms the result of an arithmetic or logical operation.
8XC196LX SUPPLEMENT byte Any 8-bit unit of data. BYTE An unsigned, 8-bit variable with values from 0 through 28–1. CCBs Chip configuration bytes. The chip configuration registers (CCRs) are loaded with the contents of the CCBs after a reset. CCRs Chip configuration registers. Registers that define the environment in which the microcontroller will be operating. The chip configuration registers are loaded with the contents of the CCBs after a reset.
GLOSSARY contention The detection of conflicting symbols or bits on the bus. crosstalk See off-isolation. DC input leakage Leakage current from an analog input pin to ground or to the reference voltage (VREF). deassert The act of making a signal inactive (disabled). The polarity (high or low) is defined by the signal name. Active-low signals are designated by a pound symbol (#) suffix; active-high signals have no suffix. To deassert RD# is to drive it high; to deassert ALE is to drive it low.
8XC196LX SUPPLEMENT external address A 21-bit address is presented on the microcontroller’s pins. The address decoded by an external device depends on how many of these address pins the external system uses. See also internal address. f Lowercase “f” represents the frequency of the internal clock. far constants Constants that can be accessed only with extended instructions. See also near constants. far data Data that can be accessed only with extended instructions. See also near data.
GLOSSARY internal address The 24-bit address that the microcontroller generates. See also external address. interrupt controller The module responsible for handling interrupts that are to be serviced by interrupt service routines that you provide. Also called the programmable interrupt controller (PIC). interrupt latency The total delay between the time that an interrupt is generated (not acknowledged) and the time that the microcontroller begins executing the interrupt service routine or PTS routine.
8XC196LX SUPPLEMENT maskable interrupts All interrupts except stack overflow, unimplemented opcode, and software trap. Maskable interrupts can be disabled (masked) by the individual mask bits in the interrupt mask registers, and their servicing can be disabled by the DI (disable interrupt service) instruction. Each maskable interrupt can be assigned to the PTS for processing.
GLOSSARY nonlinearity The maximum deviation of code transitions of the terminal-based characteristic from the corresponding code transitions of the ideal characteristic. nonmaskable interrupts Interrupts that cannot be masked (disabled) and cannot be assigned to the PTS for processing. The nonmaskable interrupts are stack overflow, unimplemented opcode, software trap, and NMI. The DI (disable interrupt service) and EI (enable interrupt service) instructions have no effect on nonmaskable interrupts.
8XC196LX SUPPLEMENT prioritized interrupt NMI, stack overflow, or any maskable interrupt. Two of the nonmaskable interrupts (unimplemented opcode and software trap) are not prioritized; they vector directly to the interrupt service routine when executed. program memory A partition of memory where instructions can be stored for fetching and execution. protected instruction An instruction that prevents an interrupt from being acknowledged until after the next instruction executes.
GLOSSARY PTS vector A location in special-purpose memory that holds the starting address of a PTS control block. QUAD-WORD An unsigned, 64-bit variable with values from 0 through 264–1. The QUAD-WORD variable is supported only as the operand for the EBMOVI instruction. quantizing error An unavoidable A/D conversion error that results simply from the conversion of a continuous voltage to its integer digital representation. Quantizing error is always ± 0.
8XC196LX SUPPLEMENT sample time uncertainty The variation in the sample time. sample window The period of time that begins when the sample capacitor is attached to a selected channel of an A/D converter and ends when the sample capacitor is disconnected from the selected channel. sampled inputs All input pins, with the exception of RESET#, are sampled inputs. The input pin is sampled one state time before the read buffer is enabled.
GLOSSARY special-purpose memory A partition of memory used for storing the interrupt vectors, PTS vectors, chip configuration bytes, and several reserved locations. standard interrupt Any maskable interrupt that is assigned to the interrupt controller for processing by an interrupt service routine. state time (or state) The basic time unit of the microcontroller; the combined period of the two internal timing signals, PH1 and PH2.
8XC196LX SUPPLEMENT VCC rejection The property of an A/D converter that causes it to ignore (reject) changes in V CC so that the actual characteristic is unaffected by those changes. The effectiveness of VCC rejection is measured by the ratio of the change in VCC to the change in the actual characteristic. VPW Variable pulse-width. A forced high/low symbol transition formatting scheme that tracks the duration between two consecutive transitions and the level of the bus, active or passive.
Index
INDEX A Address map, 3-1 Address partitions map, 3-1 OTPROM, 11-1 program memory, 11-1 special-purpose memory, 11-1 ALE, idle, powerdown, reset status, A-8, A-9 B Block diagram 8XC196Lx, 2-2 C CLKOUT and internal timing, 2-2–2-4 idle, powerdown, reset status, A-8, A-9 output frequency, 2-5 reset status, 5-2 Clock circuitry, 2-3, 10-2 D delay register, 8-20 Design considerations, 9-2 Device pin reset status, A-8, A-9 Documents, related, 1-2 E EA#, idle, powerdown, reset status, A-8, A-9 EPA interrupt mas
P Period (t), 2-4 Port 0 idle, powerdown, reset status, A-8, A-9 overview, 5-1 Port 1 configuring, 5-3 idle, powerdown, reset status, A-8, A-9 overview, 5-1 Port 2 configuring, 5-3 idle, powerdown, reset status, A-8, A-9 overview, 5-1 P2.
