Intel® Pentium® D Processor 900Δ Sequence and Intel® Pentium® Processor Extreme Edition 955, 965 Δ Specification Update - On 65 nm Process in the 775-land LGA Package supporting Intel® 64 Architecture and Intel® Virtualization Technology± May 2008 Document Number: 310307-018
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
Contents Contents .............................................................................................................................3 Revision History ...................................................................................................................4 Preface ...............................................................................................................................5 Summary Tables of Changes ......................................................................
Revision History Version Description Date -001 • Initial release -002 • Added Intel Pentium D processor 900 sequence specifications January 2006 -003 • Updated related documents, added processor number February 2006 -004 • Replaced AA5 with new erratum, added erratum AA31 March 2006 ® December 2005 ® -005 • Added Intel Pentium Processor Extreme Edition 965 Out of Cycle March 22, 2006 -006 • Added Errata AA32, AA33, AA34, added C1 step -007 • Added Pentium D processor 960 -008 • Adde
Preface Preface This document is an update to the specifications contained in the documents listed in the following Affected Documents/Related Documents table. It is a compilation of device and document errata and specification clarifications and changes, and is intended for hardware system manufacturers and for software developers of applications, operating system, and tools.
Preface Nomenclature S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics (e.g., core speed, L2 cache size, package type, etc.) as described in the processor identification information table. Care should be taken to read all notes associated with each S-Spec number QDF Number is a several digit code that is used to distinguish between engineering samples. These processors are used for qualification and early design validation.
Summary Tables of Changes Summary Tables of Changes The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed MCH steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
Summary Tables of Changes Item Numbering Each Specification Update item is prefixed with a capital letter to distinguish the product. The key below details the letters that are used in Intel’s microprocessor specification updates: A= Dual-Core Intel® Xeon® processor 7000 sequence C= Intel® Celeron® processor D= Dual-Core Intel® Xeon® processor 2.
Summary Tables of Changes AK = AL = AM = AN = AO = AP = AQ = AR = AS = AV = AW = AX = AY= AZ = AAA = AAB = AAC = AAD = AAE = Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 Quad processor Q6000 sequence Dual-Core Intel® Xeon® processor 7100 series Intel® Celeron® processor 400 sequence Intel® Pentium® dual-core processor Quad-Core Intel® Xeon® processor 3200 series Dual-Core Intel® Xeon® processor 3000 series Intel® Pentium® dual-core desktop processor E2000 sequence Intel® Cel
Summary Tables of Changes 10 NO B1 C1 D0 Plan ERRATA AA10 X X X No Fix BTS (Branch Trace Store) and PEBS(Precise Event Based Sampling) May Update Memory outside the BTS/PEBS Buffer AA11 X X X No Fix Control Register 2 (CR2) Can be Updated during a REP MOVS/STOS Instruction with Fast Strings Enabled AA12 X X X No Fix REP STOS/MOVS Instructions with RCX >=2^32 May Cause a System Hang AA13 X X X No Fix A 64-Bit Value of Linear Instruction Pointer (LIP) May be Reported Incorrectly
Summary Tables of Changes NO B1 Plan ERRATA AA30 X Fixed During an Enhanced HALT or Enhanced Intel® Speed Step Technology Ratio Transition the System May Hang AA31 X X X No Fix L2 Cache ECC Machine Check Errors May be erroneously Reported after an Asynchronous RESET# Assertion AA32 X X X Plan Fix AA33 X X X No Fix Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect Address Translations AA34 X X X No Fix Writing Shared Unaligned Data that Crosses a Cache Line witho
Summary Tables of Changes Number Plan SPECIFICATION CLARIFICATIONS There are no Specification Clarification in this Specification Update revision Number Plan DOCUMENTATION CHANGES There are no Documentation Changes in this Specification Update revision.
General Information General Information Figure 1. Intel® Pentium® D Processor 900 Sequence (Package Top Markings) Figure 2.
Identification Information Identification Information The Intel® Pentium® D processor 900 sequence and Intel® Pentium® processor Extreme Edition 955, 965 and can be identified by the following values: Family1 Model2 1111b 0110b NOTES: 1. The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan. 2.
Identification Information Table 1. Intel® Pentium® D Processor 900 Sequence and Intel® Pentium® Processor Extreme Edition 955, 965 Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Processor Number Speed Core/Bus Package Notes SL9D9 C1 2M x 2 0F64h 925 3.00GHz/800MHz 775-Land LGA 1, 3 SL9QB C1 2M x 2 0F64h 945 3.40GHz/800MHz 775-Land LGA 1, 3 SL95X C1 2M x 2 0F64h 930 3.
Errata Errata AA1. Bus Locks and SMC Detection May Cause the Processor to Hang Temporarily Problem: The processor may temporarily hang in an Hyper-Threading Technology enabled system if one logical processor executes a synchronization loop that includes one or more locks and is waiting for release by the other logical processor.
Errata AA3. Data Breakpoints on the High Half of a Floating Point Line Split May Not Be Captured Problem: When a floating point load which splits a 64-byte cache line gets a floating point stack fault, and a data breakpoint register maps to the high line of the floating point load, internal boundary conditions exist that may prevent the data breakpoint from being captured. Implication: When this erratum occurs, a data breakpoint will not be captured. Workaround: None identified.
Errata AA6. FXRSTOR May Not Restore Non-canonical Effective Addresses on Processors with Intel® Extended Memory 64 Technology (Intel® EM64T) Enabled Problem: If an x87 data instruction has been executed with a non-canonical effective address, FXSAVE may store that non-canonical FP Data Pointer (FDP) value into the save image. An FXRSTOR instruction executed with 64-bit operand size may signal a General Protection Fault (#GP) if the FDP or FP Instruction Pointer (FIP) is in non-canonical form.
Errata AA9. With TF (Trap Flag) Asserted, FP Instruction That Triggers an Unmasked FP Exception May Take Single Step Trap before Retirement of Instruction Problem: If an FP instruction generates an unmasked exception with the EFLAGS.TF=1, it is possible for external events to occur, including a transition to a lower power state. When resuming from the lower power state, it may be possible to take the single step trap before the execution of the original FP instruction completes.
Errata Implication: The value in CR2 is correct at the time that an architectural page fault is signaled. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AA12.
Errata AA14. Access to an Unsupported Address Range in Uniprocessor (UP) or Dual-processor (DP) Systems Supporting Intel® Virtualization Technology May Not Trigger Appropriate Actions Problem: When using processors supporting Intel® Virtualization Technology and configured as dual- or single-processor-capable (i.e. not multiprocessorcapable), the processor should perform address checks using a maximum physical address width of 36.
Errata AA17.
Errata AA20. A VM Exit due to SMI or INIT in Parallel with a Pending FP Exception May Not Correctly Clear the Interruptibility State Bits Problem: When a pending FP exception is ready to be taken, a VM exit due to SMI or INIT may not clear Blocking by STI and/or Blocking by MOV SS bits correctly in Virtual-Machine Control Structure (VMCS) as expected.. Implication: A VM exit due to SMI or INIT may show incorrect STI and/or MOV SS blocking state in VM-exit Interruptibility field.
Errata AA23. Machine Check Exceptions May not Update Last-Exception Record MSRs (LERs) Problem: The Last-Exception Record MSRs (LERs) may not get updated when Machine Check Exceptions occur Implication: When this erratum occurs, the LER may not contain information relating to the machine check exception. They will contain information relating to the exception prior to the machine check exception. Workaround: None identified Status: For the steppings affected, see the Summary Tables of Changes. AA24.
Errata AA26. At a Bus Ratio of 13:1, RCNT and Address Parity May be Incorrect Problem: In a system running at the 13:1 bus ratio, RCNT[0] ( ADDR# [28], phase b) may report incorrect information. Implication: RCNT[0] may contain incorrect information and cause address parity machine check errors. Workaround: Address parity should be disabled and RCNT information should be ignored at the bus ratio of 13:1. Status: For the steppings affected, see the Summary Tables of Changes. AA27.
Errata AA30. During an Enhanced HALT or Enhanced Intel SpeedStep® Technology Ratio Transition the System May Hang Problem: The BNR signal may not function properly during an Enhanced HALT or Enhanced Intel SpeedStep Technology ratio transition. Implication: The system may hang due to incorrect BNR signaling. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. AA31.
Errata AA33. Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect Address Translations Problem: An external A20M# pin if enabled forces address bit 20 to be masked (forced to zero) to emulates real-address mode address wraparound at 1 megabyte.
Errata AA35. The IA32_MC0_STATUS and IA32_MC1_STATUS Overflow Bit is not set when Multiple Un-correctable Machine Check Errors Occur at the Same Time Problem: When two enabled MC0/MC1 un-correctable machine check errors are detected in the same bank in the same internal clock cycle, the highest priority error will be logged in IA32_MC0_STATUS / IA32_MC1_STATUS register, but the overflow bit may not be set.
Errata AA38. The Processor May Issue Front Side Bus Transactions up to 6 Clocks after RESET# is Asserted Problem: The processor may issue transactions beyond the documented 3 Front Side Bus (FSB) clocks and up to 6 FSB clocks after RESET# is asserted in the case of a warm reset. A warm reset is where the chipset asserts RESET# when the system is running. Implication: The processor may issue transactions up to 6 FSB clocks after the RESET# is asserted Workaround: None identified.
Errata AA41. VMLAUNCH/VMRESUME May Not Fail when VMCS is Programmed to Cause VM Exit to Return to a Different Mode Problem: VMLAUNCH/VMRESUME instructions may not fail if the value of the “host address-space size” VM-exit control differs from the setting of IA32_EFER.LMA. Implication: Programming the VMCS to allow the monitor to be in different modes prior to VMLAUNCH/VMRESUME and after VM-exit may result in undefined behavior.
Errata Implication: Due to this erratum, FSB marginality is observed during processor core to core transactions as well as during read transactions driven by the Memory Controller Hub (MCH) leading to unpredictable system behavior. Workaround: It is possible for BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. AA45.
Specification Changes Specification Changes The Specification Changes listed in this section apply to the following documents: • Intel® Pentium® D Processor 900 Sequence and Intel® Pentium® Processor Extreme Edition 955, 965 Datasheet All Specification Changes will be incorporated into a future version of the appropriate Pentium D processor 900 sequence and Pentium processor Extreme Edition 955, 965 documentation. Δ Intel processor numbers are not a measure of performance.
Specification Clarifications Specification Clarifications The Specification Clarifications listed in this section apply to the following documents: • Intel® Pentium® D Processor 900 Sequence and Intel® Pentium® Processor Extreme Edition 955, 965 Datasheet All Specification Clarifications will be incorporated into a future version of the appropriate Pentium D processor 900 sequence and Pentium processor Extreme Edition 955, 965 documentation.
Documentation Changes Documentation Changes The Documentation Changes listed in this section apply to the following documents: • Intel® Pentium® D Processor 900 Sequence and Intel® Pentium® Processor Extreme Edition 955, 965 Datasheet All Documentation Changes will be incorporated into a future version of the appropriate Pentium D processor 900 sequence and Pentium processor Extreme Edition 955, 965 documentation.
