Intel Pentium D Processor 800 Sequence and Intel Pentium Processor Extreme Edition 840 Specification Update

Errata

Intel

Pentium

Processor Extreme Edition and

Intel

Pentium

D Processor Specification Update 39

F58. CPUID Feature Flag Reports LAHF/SAHF as Unavailable however the

Execution of LAHF/SAHF May Not Result in an Invalid Opcode Exception

Problem: As described in the IA-32 Intel

Architecture Software Developer’s Manual, support for

LAHF/SAHF instructions in 64-bit mode has been added to Intel EM64T processors. The CPUID

feature flag may indicate that the LAHF/SAHF instructions are unavailable in 64-bit mode, even

though the instructions are supported and able to be executed without an Invalid Opcode

exception.

Implication: The CPUID Feature Flag incorrectly reports LAHF/SAHF instructions as unavailable in 64-bit

mode; however they can be executed normally.

Workaround: It is possible for the BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.

F59. IRET under Certain Conditions May Cause an Unexpected Alignment Check

Exception

Problem: In IA-32e mode, it is possible to get an Alignment Check Exception (#AC) on the IRET

instruction even though alignment checks were disabled at the start of the IRET. This can only

occur if the IRET instruction is returning from CPL3 code to CPL3 code. IRETs from CPL0/1/2

are not affected. This erratum can occur if the EFLAGS value on the stack has the AC flag set,

and the interrupt handler's stack is misaligned. In IA-32e mode, RSP is aligned to a 16-byte

boundary before pushing the stack frame.

Implication: In IA-32e mode, under the conditions given above, an IRET can get a #AC even if alignment

checks are disabled at the start of the IRET. This erratum can only be observed with a software

generated stack frame.

Workaround: Software should not generate misaligned stack frames for use with IRET.

Status: For the steppings affected, see the Summary Tables of Changes.

F60. L2 Cache ECC Machine Check Errors May be erroneously Reported after an

Asynchronous RESET# Assertion

Problem: Machine check status MSRs may incorrectly report the following L2 Cache ECC machine-check

errors when cache transactions are in-flight and RESET# is asserted:

•Instruction Fetch Errors (IA32_MC2_STATUS with MCA error code 153)

•L2 Data Write Errors (IA32_MC1_STATUS with MCA error code 145)

Implication: Uncorrected or corrected L2 ECC machine check errors may be erroneously reported. Intel has

not observed this erratum on any commercially available system.

Workaround: When a real run-time L2 Cache ECC Machine Check occurs, a corresponding valid error will

normally be logged in the IA32_MC0_STATUS register. BIOS may clear IA32_MC2_STATUS

and/or IA32_MC1_STATUS for these specific errors when IA32_MC0_STATUS does not have

its VAL flag set.

Status: For the steppings affected, see the Summary Tables of Changes.