Intel Pentium D Processor 800 Sequence and Intel Pentium Processor Extreme Edition 840 Specification Update

Errata

38 Intel

Pentium

Processor Extreme Edition and

Intel

Pentium

D Processor Specification Update

F55. The Processor May Issue Front Side Bus Transactions up to 6 Clocks after

RESET# is Asserted

Problem: The processor may issue transactions beyond the documented 3 Front Side Bus (FSB) clocks and

up to 6 FSB clocks after RESET# is asserted in the case of a warm reset. A warm reset is where

the chipset asserts RESET# when the system is running.

Implication: The processor may issue transactions up to 6 FSB clocks after RESET# is asserted

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

F56. Front Side Bus Machine Checks May be Reported as a Result of On-Going

Transactions during Warm Reset

Problem: Processor Front Side Bus (FSB) protocol/signal integrity machine checks may be reported if the

transactions are initiated or in-progress during a warm reset. A warm reset is where the chipset

asserts RESET# when the system is running.

Implication: The processor may log FSB protocol/signal integrity machine checks if transactions are allowed

to occur during RESET# assertions.

Workaround: BIOS may clear FSB protocol/signal integrity machine checks for systems/chipsets which do not

block new transactions during RESET# assertions.

Status: For the steppings affected, see the Summary Tables of Changes.

F57. Writing the Local Vector Table (LVT) when an Interrupt is Pending May

Cause an Unexpected Interrupt

Problem: If a local interrupt is pending when the LVT entry is written, an interrupt may be taken on the

new interrupt vector even if the mask bit is set.

Implication: An interrupt may immediately be generated with the new vector when a LVT entry is written,

even if the new LVT entry has the mask bit set. If there is no Interrupt Service Routine (ISR) set

up for that vector the system will GP fault. If the ISR does not do an End of Interrupt (EOI) the

bit for the vector will be left set in the in-service register and mask all interrupts at the same or

lower priority.

Workaround: Any vector programmed into an LVT entry must have an ISR associated with it, even if that

vector was programmed as masked. This ISR routine must do an EOI to clear any unexpected

interrupts that may occur. The ISR associated with the spurious vector does not generate an EOI;

therefore the spurious vector should not be used when writing the LVT.

Status: For the steppings affected, see the Summary Tables of Changes.