Intel Pentium D Processor 800 Sequence and Intel Pentium Processor Extreme Edition 840 Specification Update

Errata

Intel

Pentium

Processor Extreme Edition and

Intel

Pentium

D Processor Specification Update 37

F52. Voltage and Frequency Transition May Not Occur if a Voltage Transition is

Interrupted by a Warm Reset

Problem: In an Enhanced Intel SpeedStep

Technology or Thermal Monitor 2 enabled system, if a voltage

and frequency transition is interrupted by a warm reset and the next transition is to a higher

voltage and frequency then that transition and all subsequent transitions will not be performed.

Implication: When this erratum occurs, the processor will not perform any further transitions and will remain

at the Reset# voltage and frequency. Intel has not observed this erratum with any commercially

available system.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

F53. It is Possible That Two specific Invalid Opcodes May Cause Unexpected

Memory Accesses

Problem: A processor is expected to respond with an undefined opcode (#UD) fault when executing either

opcode 0F 78 or a Grp 6 Opcode with bits 5:3 of the Mod/RM field set to 6, however the

processor may respond instead, with a load to an incorrect address.

Implication: This erratum may cause unpredictable system behavior or system hang.

Workaround: It is possible for BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.

F54. At Core-to-bus Ratios of 16:1 and Above Defer Reply Transactions with

Non-zero REQb Values May Cause a Front Side Bus Stall

Problem: Certain processors are likely to hang the Front Side Bus (FSB) if the following conditions are

met:

1. A Defer Reply transaction has a REQb[2:0] value of either 010b, 011b, 100b, 110b, or 111b,

and

2. The operating bus ratio is 16:1 or higher.

When these conditions are met, the processor may incorrectly and indefinitely assert a snoop stall

for the Defer Reply transaction. Such an event will block further progress on the FSB.

Implication: If this erratum occurs, the system may hang. Intel chipsets avoid the REQb conditions required to

observe this erratum.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.