Intel Pentium D Processor 800 Sequence and Intel Pentium Processor Extreme Edition 840 Specification Update

Errata

36 Intel

Pentium

Processor Extreme Edition and

Intel

Pentium

D Processor Specification Update

F49. Incorrect Duty Cycle is Chosen when On-Demand Clock Modulation Is

Enabled in a Processor Supporting Hyper-Threading Technology

Problem: When a processor supporting Hyper-Threading Technology enables On-Demand Clock

Modulation on both logical processors, the processor is expected to select the lowest duty cycle of

the two potentially different values. When one logical processor enters the AUTOHALT state, the

duty cycle implemented should be unaffected by the halted logical processor. Due to this erratum,

the duty cycle is incorrectly chosen to be the higher duty cycle of both logical processors.

Implication: Due to this erratum, higher duty cycle may be chosen when the On-Demand Clock Modulation is

enabled on both logical processors.

Workaround: None identified at this time

Status: For the steppings affected, see the Summary Tables of Changes.

F50. Enhanced Halt State (C1E) May Not Be Entered in a System with More Than

One Logical Processor

Problem: If the IA32_MISC_ENABLE MSR (0x1A0) C1E enable bit is not set prior to an INIT event on a

system with more than one logical processor, the processor will not enter C1E until the next SIPI

wakeup event for the logical processor in the "Wait-for-SIPI" state.

Implication: Due to this erratum, the processor will not enter C1E state.

Workaround: If C1E is supported in the system, the IA32_MISC_ENABLE MSR should be enabled prior to

issuing the first SIPI to another logical processor.

Status: For the steppings affected, see the Summary Tables of Changes.

F51. A 64-Bit Value of Linear Instruction Pointer (LIP) May be Reported

Incorrectly in the Branch Trace Store (BTS) Memory Record or in the

Precise Event Based Sampling (PEBS) Memory Record

Problem: On a processor supporting Intel

EM64T,

• If an instruction fetch wraps around the 4G boundary in Compatibility Mode, the 64-bit value

of LIP in the BTS memory record will be incorrect (upper 32 bits will be set to FFFFFFFFh

when they should be 0).

• If a PEBS event occurs on an instruction whose last byte is at memory location FFFFFFFFh,

the 64-bit value of LIP in the PEBS record will be incorrect (upper 32 bits will be set to

FFFFFFFFh when they should be 0).

Implication: Intel has not observed this erratum on any commercially available software.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.