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Intel Pentium D Processor 800 Sequence and Intel Pentium Processor Extreme Edition 840 Specification Update

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D Processor Specification Update 35
F46. A Data Access which Spans Both the Canonical and the Non-Canonical
Address Space May Hang the System
Problem: If a data access causes a page split across the canonical to non-canonical address space the
processor may livelock which in turn would cause a system hang.
Implication: When this erratum occurs, the processor may livelock, resulting in a system hang. Intel has not
observed this erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
F47. Running in SMM (System Management Mode) And L1 Data Cache Adaptive
Mode May Cause Unexpected System Behavior when SMRAM is Mapped to
Cacheable Memory
Problem: In a Hyper-Threading Technology-enabled system, unexpected system behavior may occur if a
change is made to the value of the CR3 result from an RSM (Resume From System Management)
instruction while in L1 data cache adaptive mode (IA32_MISC_ENABLES MSR 0x1a0, bit 24).
This behavior will only be visible when SMRAM is mapped into WB/WT cacheable memory on
SMM entry and exit.
Implication: This erratum can have multiple failure symptoms including incorrect data in memory. Intel has
not observed this erratum with any commercially available software.
Workaround: Disable L1 data cache adaptive mode by setting the L1 Data Cache Context Mode control (bit 24)
of the IA32_MISC_ENABLES MSR (0x1a0) to 1.
Status: For the steppings affected, see the Summary Tables of Changes.
F48. Entering Single Logical Processor Mode Via Power on Configuration
Results in a System Hang at Reset
Problem: When the system uses power on configuration (POC) to enter single logical processor mode on a
dual core processor (by asserting A31# at the deassertion of RESET#), the system will hang at
reset.
Implication: POC can not be used to enter single logical processor mode.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.