Intel Pentium D Processor 800 Sequence and Intel Pentium Processor Extreme Edition 840 Specification Update

Errata

Intel

Pentium

Processor Extreme Edition and

Intel

Pentium

D Processor Specification Update 33

F41. Memory Ordering Failure May Occur with Snoop Filtering Third Party

Agents after Issuing and Completing a BWIL (Bus Write Invalidate Line) or

BLW (Bus Locked Write) Transaction

Problem: Under limited circumstances, the processors may, after issuing and completing a BWIL or BLW

transaction, retain data from the addressed cache line in shared state even though the specification

requires complete invalidation. This data retention may also occur when a BWIL transaction’s

self-snooping yields HITM snoop results.

Implication: A system may suffer memory ordering failures if its central agent incorporates coherence

sequencing which depends on full self-invalidation of the cache line associated (1) with BWIL

and BLW transactions, or (2) all HITM snoop results without regard to the transaction type and

snoop results source.

Workaround: 1. The central agent can issue a bus cycle that causes a cache line to be invalidated (Bus Read

Invalidate Line (BRIL) or BWIL transaction) in response to a processor-generated BWIL (or

BLW) transaction to insure complete invalidation of the associated cache line. If there are no

intervening processor-originated transactions to that cache line, the central agent’s invalidating

snoop will get a clean snoop result.

2. Snoop filtering central agents can:

a. Not use processor-originated BWIL or BLW transactions to update their snoop filter

information, or

b. Update the associated cache line state information to shared state on the originating bus

(rather than invalid state) in reaction to a BWIL or BLW.

Status: For the steppings affected, see the Summary Tables of Changes.

F42. Control Register 2 (CR2) Can be Updated during a REP MOVS/STOS

Instruction with Fast Strings Enabled

Problem: Under limited circumstances while executing a REP MOVS/STOS string instruction, with fast

strings enabled, it is possible for the value in CR2 to be changed as a result of an interim paging

event, normally invisible to the user. Any higher priority architectural event that arrives and is

handled while the interim paging event is occurring may see the modified value of CR2.

Implication: The value in CR2 is correct at the time that an architectural page fault is signaled. Intel has not

observed this erratum with any commercially available software.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.