Intel Pentium D Processor 800 Sequence and Intel Pentium Processor Extreme Edition 840 Specification Update

Errata

32 Intel

Pentium

Processor Extreme Edition and

Intel

Pentium

D Processor Specification Update

F39. The Base of an LDT (Local Descriptor Table) Register May be Non-zero on

a Processor Supporting Intel

Extended Memory 64 Technology (Intel

EM64T)

Problem: In IA-32e mode of an Intel EM64T-enabled processor, the base of an LDT register may be non-

zero.

Implication: Due to this erratum, Intel EM64T-enabled systems may encounter unexpected behavior when

accessing an LDT register using the null selector. There may be no #GP fault in response to this

access.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

F40. L-bit of the CS and LMA bit of the IA32_EFER Register May Have an

Erroneous Value For One Instruction Following a Mode Transition in a

Hyper-Threading Enabled Processor Supporting Intel

Extended Memory

64 Technology (Intel

EM64T)

Problem: In an Intel

EM64T enabled Processor, the L-bit of the Code Segment (CS) descriptor may not

update with the correct value in an HT environment. This may occur in a small window when one

logical processor is making a transition from compatibility mode to 64-bit mode (or vice-versa)

while the other logical processor is being stalled. A similar problem may occur for the

observation of the EFER.LMA bit by the decode logic.

Implication: The first instruction following a mode transition may be decoded as if it was still in the previous

mode. For example, this may result in an incorrect stack size used for a stack operation, i.e. a

write of only 4-bytes and an adjustment to ESP of only 4 in 64-bit mode. The problem can

manifest itself, however, on any instruction which would behave differently in 64-bit mode than

in compatibility mode.

Workaround: It is possible for the BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.