Intel Pentium D Processor 800 Sequence and Intel Pentium Processor Extreme Edition 840 Specification Update

Errata
R
Intel
®
Pentium
®
Processor Extreme Edition and
Intel
®
Pentium
®
D Processor Specification Update 29
F30. Execution of IRET or INTn Instructions May Cause Unexpected System
Behavior
Problem: There is a small window of time, requiring alignment of many internal micro architectural events,
during which the speculative execution of the IRET or INTn instructions in protected or IA-32e
mode may result in unexpected software or system behavior.
Implication: This erratum may result in unexpected instruction execution, events, interrupts or a system hang
when the IRET instruction is executed. The execution of the INTn instruction may cause debug
breakpoints to be missed.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
F31. Processor May Fault When the Upper 8 Bytes of Segment Selector Is
Loaded from a Far Jump through a Call Gate via the Local Descriptor Table
Problem: In IA-32e mode of the Intel EM64T processor, control transfers through a call gate via the Local
Descriptor Table (LDT) that uses a 16-byte descriptor, the upper 8-byte access may wrap and
access an incorrect descriptor in the LDT. This only occurs on an LDT with a LIMIT>0x10008
with a 16-byte descriptor that has a selector of 0xFFFC.
Implication: In the event this erratum occurs, the upper 8-byte access may wrap and access an incorrect
descriptor within the LDT, potentially resulting in a fault or system hang. Intel has not observed
this erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
F32. Loading a Stack Segment with a Selector that References a Non-canonical
Address Can Lead to a #SS Fault on a Processor Supporting Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
Problem: When a processor supporting Intel EM64T is in IA-32e mode, loading a stack segment with a
selector which references a non-canonical address will result in a #SS fault instead of a #GP fault.
Implication: When this erratum occurs, Intel EM64T enabled systems may encounter unexpected behavior.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.