Intel Pentium D Processor 800 Sequence and Intel Pentium Processor Extreme Edition 840 Specification Update

Errata

28 Intel

Pentium

Processor Extreme Edition and

Intel

Pentium

D Processor Specification Update

F26. Data Breakpoints on the High Half of a Floating Point Line Split May Not Be

Captured

Problem: When a floating point load which splits a 64-byte cache line gets a floating point stack fault, and a

data breakpoint register maps to the high line of the floating point load, internal boundary

conditions exist that may prevent the data breakpoint from being captured.

Implication: When this erratum occurs, a data breakpoint will not be captured.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

F27. Machine Check Exceptions May not Update Last-Exception Record MSRs

(LERs)

Problem: The Last-Exception Record MSRs (LERs) may not get updated when Machine Check Exceptions

occur.

Implication: When this erratum occurs, the LER may not contain information relating to the machine check

exception. They will contain information relating to the exception prior to the machine check

exception.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

F28. MOV CR3 Performs Incorrect Reserved Bit Checking When in PAE Paging

Problem: The MOV CR3 instruction should perform reserved bit checking on the upper unimplemented

address bits. This checking range should match the address width reported by CPUID instruction

0x8000008. This erratum applies whenever PAE is enabled.

Implication: Software that sets the upper address bits on a MOV CR3 instruction and expects a fault may fail.

This erratum has not been observed with commercially available software.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

F29. Stores to Page Tables May Not Be Visible to Pagewalks for Subsequent

Loads without Serializing or Invalidating the Page Table Entry

Problem: Under rare timing circumstances, a page table load on behalf of a programmatically younger

memory access may not get data from a programmatically older store to the page table entry if

there is not a fencing operation or page translation invalidate operation between the store and the

younger memory access. Refer to the IA-32 Intel

Architecture Software Developer's Manual for

the correct way to update page tables. Software that conforms to the Software Developer's

Manual will operate correctly.

Implication: If the guidelines in the Software Developer's Manual are not followed, stale data may be loaded

into the processor's Translation Lookaside Buffer (TLB) and used for memory operations. This

erratum has not been observed with any commercially available software.

Workaround: The guidelines in the IA-32 Intel

Architecture Software Developer's Manual should be followed.

Status: For the steppings affected, see the Summary Tables of Changes.