Intel Pentium D Processor 800 Sequence and Intel Pentium Processor Extreme Edition 840 Specification Update

Errata

Intel

Pentium

Processor Extreme Edition and

Intel

Pentium

D Processor Specification Update 27

F23. Interactions between the Instruction Translation Lookaside Buffer (ITLB)

and the Instruction Streaming Buffer May Cause Unpredictable Software

Behavior

Problem: Complex interactions within the instruction fetch/decode unit may make it possible for the

processor to execute instructions from an internal streaming buffer containing stale or incorrect

information.

Implication: When this erratum occurs, an incorrect instruction stream may be executed resulting in

unpredictable software behavior.

Workaround: It is possible for the BIOS to contain a workaround for this erratum.

Status: For the stepping affected, see the Summary Tables of Changes.

F24. Using STPCLK# and Executing Code from Very Slow Memory Could Lead

to a System Hang

Problem: The system may hang when the following conditions are met:

1. Periodic STPCLK# mechanism is enabled via the chipset

2. Hyper-Threading Technology is enabled

3. One logical processor is waiting for an event (i.e. hardware interrupt)

4. The other logical processor executes code from very slow memory such that every code fetch

is deferred long enough for the STPCLK to be re-asserted.

Implication: If this erratum occurs, the processor will go into and out of the sleep state without making

forward progress, since the logical processor will not be able to service any pending event. This

erratum has not been observed in any commercial platform running commercial software.

Workaround: None

Status: For the steppings affected, see the Summary Tables of Changes.

F25. Processor Provides a 4-Byte Store Unlock after an 8-Byte Load Lock

Problem: When the processor is in the Page Address Extension (PAE) mode and detects the need to set the

Access and/or Dirty bits in the page directory or page table entries, the processor sends an 8 byte

load lock onto the system bus. A subsequent 8 byte store unlock is expected, but instead a 4 byte

store unlock occurs. Correct data is provided since only the lower bytes change, however external

logic monitoring the data transfer may be expecting an 8 byte load lock.

Implication: No known commercially available chipsets are affected by this erratum.

Workaround: None identified at this time.

Status: For the steppings affected, see the Summary Tables of Changes.