Intel Pentium D Processor 800 Sequence and Intel Pentium Processor Extreme Edition 840 Specification Update

Errata

26 Intel

Pentium

Processor Extreme Edition and

Intel

Pentium

D Processor Specification Update

F20. Incorrect Debug Exception (#DB) May Occur When a Data Breakpoint Is Set

on an FP Instruction

Problem: The default Microcode Floating Point Event Handler routine executes a series of loads to obtain

data about the FP instruction that is causing the FP event. If a data breakpoint is set on the

instruction causing the FP event, the load in the microcode routine will trigger the data breakpoint

resulting in a Debug Exception.

Implication: An incorrect Debug Exception (#DB) may occur if data breakpoint is placed on an FP instruction.

Intel has not observed this erratum with any commercially available software or system.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

F21. xAPIC May Not Report Some Illegal Vector Errors

Problem: The local xAPIC has an Error Status Register, which records all errors. The bit 6 (the Receive

Illegal Vector bit) of this register, is set when the local xAPIC detects an illegal vector in a

received message. When an illegal vector error is received on the same internal clock that the

error status register is being written (due to a previous error), bit 6 does not get set and illegal

vector errors are not flagged

Implication: The xAPIC may not report some Illegal Vector errors when they occur at approximately the same

time as other xAPIC errors. The other xAPIC errors will continue to be reported.

Workaround: None identified

Status: For the stepping affected, see the Summary Tables of Changes.

F22. Memory Aliasing of Pages As Uncacheable Memory Type and Write Back

(WB) May Hang the System

Problem: When a page is being accessed as either Uncacheable (UC) or Write Combining (WC) and WB,

under certain bus and memory timing conditions, the system may loop in a continual sequence of

UC fetch, implicit writeback, and Request For Ownership (RFO) retries.

Implication: This erratum has not been observed in any commercially available operating system or

application. The aliasing of memory regions, a condition necessary for this erratum to occur, is

documented as being unsupported in the IA-32 Intel

Architecture Software Developer's Manual,

Volume 3, section 10.12.4, Programming the PAT. However, if this erratum occurs the system

may hang.

Workaround: The pages should not be mapped as either UC or WC and WB at the same time.

Status: For the stepping affected, see the Summary Tables of Changes.