Intel Pentium D Processor 800 Sequence and Intel Pentium Processor Extreme Edition 840 Specification Update

Errata
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Intel
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Pentium
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Processor Extreme Edition and
Intel
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Pentium
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D Processor Specification Update 25
F17. A Write to an APIC Registers Sometimes May Appear to Have Not Occurred
Problem: With respect to the retirement of instructions, stores to the uncacheable memory-based APIC
register space are handled in a non-synchronized way. For example if an instruction that masks
the interrupt flag, e.g. CLI, is executed soon after an uncacheable write to the Task Priority
Register (TPR) that lowers the APIC priority, the interrupt masking operation may take effect
before the actual priority has been lowered. This may cause interrupts whose priority is lower
than the initial TPR, but higher than the final TPR, to not be serviced until the interrupt enabled
flag is finally set, i.e. by STI instruction. Interrupts will remain pending and are not lost.
Implication: In this example the processor may allow interrupts to be accepted but may delay their service.
Workaround: This non-synchronization can be avoided by issuing an APIC register read after the APIC register
write. This will force the store to the APIC register before any subsequent instructions are
executed. No commercial operating system is known to be impacted by this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
F18. Parity Error in the L1 Cache May Cause the Processor to Hang
Problem: If a locked operation accesses a line in the L1 cache that has a parity error, it is possible that the
processor may hang while trying to evict the line.
Implication: If this erratum occurs, it may result in a system hang. Intel has not observed this erratum with any
commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
F19. Bus Locks and SMC Detection May Cause the Processor to Hang
Temporarily
Problem: The processor may temporarily hang in an HT Technology enabled system if one logical
processor executes a synchronization loop that includes one or more locks and is waiting for
release by the other logical processor. If the releasing logical processor is executing instructions
that are within the detection range of the self -modifying code (SMC) logic, then the processor
may be locked in the synchronization loop until the arrival of an interrupt or other event.
Implication: If this erratum occurs in an HT Technology enabled system, the application may temporarily stop
making forward progress. Intel has not observed this erratum with any commercially available
software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.