Intel Pentium D Processor 800 Sequence and Intel Pentium Processor Extreme Edition 840 Specification Update

Summary Tables of Changes
R
12 Intel
®
Pentium
®
Processor Extreme Edition and
Intel
®
Pentium
®
D Processor Specification Update
NO. A0 B0 Plan ERRATA
F35 X X No Fix
Checking of Page Table Base Address May Not Match the Address Bit
Width Supported by the Platform
F36 X X No Fix
The IA32_MCi_STATUS MSR May Improperly Indicate that Additional
MCA Information May Have Been Captured
F37 X X No Fix
With TF (Trap Flag) Asserted, FP Instruction That Triggers an
Unmasked FP Exception May Take Single Step Trap Before Retirement
of Instruction
F38 X X No Fix
BTS(Branch Trace Store) and PEBS(Precise Event Based Sampling)
May Update Memory outside the BTS/PEBS Buffer
F39 X Plan Fix
The Base of an LDT (Local Descriptor Table) Register May be Non-zero
on a Processor Supporting Intel
®
Extended Memory 64 Technology
(Intel
®
EM64T)
F40 X
1
X
1
Plan Fix
L-bit of the CS and LMA bit of the IA32_EFER Register May Have an
Erroneous Value For One Instruction Following a Mode Transition in a
Hyper-Threading Enabled Processor Supporting Intel
®
Extended
Memory 64 Technology (Intel
®
EM64T).
F41 X X No Fix
Memory Ordering Failure May Occur with Snoop Filtering Third Party
Agents after Issuing and Completing a BWIL (Bus Write Invalidate Line)
or BLW (Bus Locked Write) Transaction
F42 X X No Fix
Control Register 2 (CR2) Can be Updated during a REP MOVS/STOS
Instruction with Fast Strings Enabled
F43 X X No Fix
REP STOS/MOVS Instructions with RCX >=2^32 May Cause a System
Hang
F44 X X Plan Fix
An REP MOVS or an REP STOS Instruction with RCX >= 2^32 May Fail
to Execute to Completion or May Write to Incorrect Memory Locations
on Processors Supporting Intel
®
Extended Memory 64 Technology
(Intel
®
EM64T)
F45 X X Plan Fix
An REP LODSB or an REP LODSD or an REP LODSQ Instruction with
RCX >= 2^32 May Cause a System Hang on Processors Supporting
Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
F46 X X No Fix
A Data Access which Spans Both the Canonical and the Non-Canonical
Address Space May Hang the System
F47 X
1
X
1
Plan Fix
Running in SMM (System Management Mode) And L1 Data Cache
Adaptive Mode May Cause Unexpected System Behavior when SMRAM
is Mapped to Cacheable Memory
F48 X X Plan Fix
Entering Single Logical Processor Mode Via Power on Configuration
Results in a System Hang at Reset
F49 X
1
X
1
No Fix
Incorrect Duty Cycle is Chosen when On-Demand Clock Modulation is
Enabled in a Processor Supporting Hyper-Threading Technology
F50 X X No Fix
Enhanced Halt State (C1E) May Not Be Entered in a System with More
Than One Logical Processor
F51 X X No Fix
A 64-Bit Value of Linear Instruction Pointer (LIP) May be Reported
Incorrectly in the Branch Trace Store (BTS) Memory Record or in the
Precise Event Based Sampling (PEBS) Memory Record
F52 X X No Fix
Voltage and Frequency Transition May Not Occur if a Voltage Transition
is Interrupted by a Warm Reset