Intel Pentium D Processor 800 Sequence and Intel Pentium Processor Extreme Edition 840 Specification Update

Summary Tables of Changes
R
Intel
®
Pentium
®
Processor Extreme Edition and
Intel
®
Pentium
®
D Processor Specification Update 11
NO. A0 B0 Plan ERRATA
F13 X X No Fix
When the Processor Is in the System Management Mode (SMM),
Debug Registers May Be Fully Writeable
F14 X X No Fix
Shutdown and IERR# May Result Due to a Machine Check Exception
on a System with More Than One Logical Processor
F15 X X No Fix
Processor May Hang under Certain Frequencies and 12.5% STPCLK#
Duty Cycle
F16 X X No Fix
System May Hang if a Fatal Cache Error Causes Bus Write Line (BWL)
Transaction to Occur to the Same Cache Line Address as an
Outstanding Bus Read Line (BRL) or Bus Read-Invalidate Line (BRIL}
F17 X X No Fix
A Write to an APIC Registers Sometimes May Appear to Have Not
Occurred
F18 X X No Fix Parity Error in the L1 Cache May Cause the Processor to Hang
F19 X X No Fix
Bus Locks and SMC Detection May Cause the Processor to
Temporarily Hang
F20 X X No Fix
Incorrect Debug Exception (#DB) May Occur When a Data Breakpoint is
set on an FP Instruction
F21 X X No Fix xAPIC May Not Report Some Illegal Vector Errors
F22 X X No Fix
Memory Aliasing of Pages as Uncacheable Memory Type and Write
Back (WB) May Hang the System
F23 X X No Fix
Interactions Between the Instruction Translation Lookaside Buffer (ITLB)
and the Instruction Streaming Buffer May Cause Unpredictable
Software Behavior
F24 X
1
X
1
No Fix
Using STPCLK# and Executing Code From Very Slow Memory Could
Lead to a System Hang
F25 X X No Fix Processor Provides a 4-Byte Store Unlock After an 8-Byte Load Lock
F26 X X No Fix
Data Breakpoints on the High Half of a Floating Point Line Split may not
be Captured
F27 X X No Fix
Machine Check Exceptions May not Update Last-Exception Record
MSRs (LERs)
F28 X X No Fix
MOV CR3 Performs Incorrect Reserved Bit Checking When in PAE
Paging
F29 X X No Fix
Stores to Page Tables May Not Be Visible to Pagewalks for Subsequent
Loads Without Serializing or Invalidating the Page Table Entry
F30 X X Plan Fix
Execution of IRET or INTn Instructions May Cause Unexpected System
Behavior
F31 X X No Fix
Processor May Fault when the Upper 8 Bytes of Segment Selector is
Loaded From a Far Jump Through a Call Gate via the Local Descriptor
Table
F32 X X No Fix
Loading a Stack Segment with a Selector that References a Non-
canonical Address can Lead to a #SS Fault on a Processor Supporting
Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
F33 X X No Fix
FXRSTOR May Not Restore Non-canonical Effective Addresses on
Processors with Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
Enabled
F34 X X No Fix A Push of ESP that Faults may Zero the Upper 32 Bits of RSP