Intel Pentium D Processor 800 Sequence and Intel Pentium Processor Extreme Edition 840 Specification Update

Summary Tables of Changes
R
10 Intel
®
Pentium
®
Processor Extreme Edition and
Intel
®
Pentium
®
D Processor Specification Update
N = Intel
®
Pentium
®
4 processor
O = Intel
®
Xeon
®
processor MP
P = Intel
®
Xeon
®
processor
Q = Mobile Intel
®
Pentium
®
4 processor supporting Hyper-Threading Technology on 90-nm
process technology
R = Intel
®
Pentium
®
4 processor on 90 nm process
S = 64-bit Intel
®
Xeon
®
processor with 800 MHz system bus (1 MB and 2 MB L2 cache versions)
T = Mobile Intel
®
Pentium
®
4 processor-M
U = 64-bit Intel
®
Xeon
®
processor MP with up to 8 MB L3 Cache
V = Mobile Intel
®
Celeron
®
processor on .13 Micron Process in Micro-FCPGA Package
W= Intel
®
Celeron-M processor
X = Intel
®
Pentium
®
M processor on 90nm process with 2-MB L2 Cache
Y = Intel
®
Pentium
®
M processor
Z = Mobile Intel
®
Pentium
®
4 processor with 533 MHz system bus
AA = Intel
®
Pentium
®
processor Extreme Edition and Intel
®
Pentium
®
D processor on 65nm
process
AB = Intel
®
Pentium
®
4 processor on 65 nm process
AC = Intel
®
Celeron
®
Processor in 478 Pin Package
AD = Intel
®
Celeron
®
D processor on 65 nm process
AE = Intel
®
Core™ Duo Processor and Intel
®
Core™ Solo processor on 65nm process
The Specification Updates for the Pentium
®
processor, Pentium
®
Pro processor, and other Intel
products do not use this convention.
NO. A0 B0 Plan ERRATA
F1 X X No Fix Transaction Is Not Retried after BINIT#
F2 X X No Fix Invalid Opcode 0FFFh Requires a ModRM Byte
F3 X X No Fix
Processor May Hang Due to Speculative Page Walks to Non-Existent
System Memory
F4 X X No Fix
Memory Type of the Load Lock Different from Its Corresponding Store
Unlock
F5 X X No Fix
Machine Check Architecture Error Reporting and Recovery May Not
Work As Expected
F6 X X No Fix Debug Mechanisms May Not Function as Expected
F7 X X No Fix
Cascading of Performance Counters Does Not Work Correctly When
Forced Overflow Is Enabled
F8 X X No Fix EMON Event Counting of x87 Loads May Not Work As Expected
F9 X X No Fix
System Bus Interrupt Messages without Data Which Receive a
HardFailure Response May Hang the Processor
F10 X X No Fix
The Processor Signals Page-Fault Exception (#PF) Instead of
Alignment Check Exception (#AC) on an Unlocked CMPXCHG8B
Instruction
F11 X X No Fix
FSW May Not Be Completely Restored after Page Fault on FRSTOR or
FLDENV Instructions
F12 X X No Fix
Processor Issues Inconsistent Transaction Size Attributes for Locked
Operation