R Intel® Pentium® D Processor 800Δ Sequence and Intel® Pentium® Processor Extreme Edition 840 Δ Specification Update September 2006 Notice: The Intel® Pentium® Processor Extreme Edition and Intel® Pentium® D Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
R INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
R Contents Revision History .................................................................................................................. 5 Preface................................................................................................................................ 7 Summary Tables of Changes ............................................................................................. 9 General Information ......................................................................................
R 4 Intel® Pentium® Processor Extreme Edition and Intel® Pentium® D Processor Specification Update
Revision History R Revision History Version Description -001 Initial release -002 Added errata F52 Date April 2005 ® May 2005 ® -003 Added the Intel Pentium D processor to this Specification Update May 2005 -004 No updates June 2005 -005 Added Erratum F53, Added Specification Clarification F1 July 2005 -006 Added Erratum F54 -007 Added Errata F55, F56 -008 Added B-step information, and added Errata F57, F58 -009 Added Errata F59 -010 Updated erratum F17, updated Figure 1 to show
Revision History R 6 Intel® Pentium® Processor Extreme Edition and Intel® Pentium® D Processor Specification Update
Preface R Preface This document is an update to the specifications contained in the documents listed in the following Affected Documents/Related Documents table. It is a compilation of device and document errata and specification clarifications and changes, and is intended for hardware system manufacturers and for software developers of applications, operating system, and tools.
Preface R Nomenclature S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics (e.g., core speed, L2 cache size, package type, etc.) as described in the processor identification information table. Care should be taken to read all notes associated with each S-Spec number Errata are design defects or errors. Errata may cause the processor’s behavior to deviate from published specifications.
Summary Tables of Changes R Summary Tables of Changes The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes that apply to the listed component steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
Summary Tables of Changes R N = Intel® Pentium® 4 processor O = Intel® Xeon® processor MP P = Intel® Xeon® processor Q = Mobile Intel® Pentium® 4 processor supporting Hyper-Threading Technology on 90-nm process technology R = Intel® Pentium® 4 processor on 90 nm process S = 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache versions) T = Mobile Intel® Pentium® 4 processor-M U = 64-bit Intel® Xeon® processor MP with up to 8 MB L3 Cache V = Mobile Intel® Celeron® processor on .
Summary Tables of Changes R NO. A0 B0 Plan F13 X X No Fix When the Processor Is in the System Management Mode (SMM), Debug Registers May Be Fully Writeable F14 X X No Fix Shutdown and IERR# May Result Due to a Machine Check Exception on a System with More Than One Logical Processor F15 X X No Fix Processor May Hang under Certain Frequencies and 12.
Summary Tables of Changes R 12 NO.
Summary Tables of Changes R NO.
General Information R General Information Figure 1. Intel® Pentium® Processor Extreme Edition and Intel® Pentium® D Processor Package Brand Processor Number/S-Spec/ Country of Assy Frequency/L2 Cache/Bus/ 775_VR_CONFIG_05x FPO INTEL m © ‘04 XXXXXXXX 840 SLxxx [COO] 3.20GHZ/2M/800/05B [FPO] [e4] Pb-free SLI designator 2-D Matrix Mark Unique Unit Identifier ATPO Serial # ATPO S/N Figure 2.
Identification Information R Identification Information The Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor can be identified by the following values: Family1 Model2 1111b 0100b NOTES: 1. The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan. 2.
Identification Information R Table 1. Intel® Pentium® Processor Extreme Edition and Intel® Pentium® D Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Processor Number Speed Core/Bus SL8CN B0 1M x 2 0F47h 830 3GHz/800MHz 775-land FCLGA4 37.5 x 2, 3, 5 37.5 mm Rev 01 SL8CM B0 1M x 2 0F47h 840 3.20GHz/800MHz 775-land FCLGA4 37.5 x 2, 3, 5 37.5 mm Rev 01 Package and Revision Notes NOTES: 1.
Errata R Errata F1. Transaction Is Not Retried after BINIT# Problem: If the first transaction of a locked sequence receives a HITM# and DEFER# during the snoop phase it should be retried and the locked sequence restarted. However, if BINIT# is also asserted during this transaction, it will not be retried. Implication: When this erratum occurs, locked transactions will unexpectedly not be retried. Workaround: None identified. Status: For the steppings affected see the Summary Tables of Changes. F2.
Errata R F4. Memory Type of the Load Lock Different from Its Corresponding Store Unlock Problem: A use-once protocol is employed to ensure that the processor in a multi-agent system may access data that is loaded into its cache on a Read-for-Ownership operation at least once before it is snooped out by another agent. This protocol is necessary to avoid a multi-agent livelock scenario in which the processor cannot gain ownership of a line and modify it before that data is snooped out by another agent.
Errata R • When one-half of a 64-byte instruction fetch from the L2 cache has an uncorrectable error and the other 32-byte half of the same fetch from the L2 cache has a correctable error, the processor will attempt to correct the correctable error but cannot proceed due to the uncorrectable error. When this occurs the processor will hang.
Errata R • The Overflow Error bit (bit 62) in the IA32_MC0_STATUS register indicates, when set, that a machine check error occurred while the results of a previous error were still in the error reporting bank (i.e. The Valid bit was set when the new error occurred). If an uncorrectable error is logged in the error-reporting bank and another error occurs, the overflow bit will not be set.
Errata R F6. Debug Mechanisms May Not Function As Expected Problem: Certain debug mechanisms may not function as expected on the processor.
Errata R F8. EMON Event Counting of x87 Loads May Not Work As Expected Problem: If a performance counter is set to count x87 loads and floating point exceptions are unmasked, the FPU Operand Data Pointer (FDP) may become corrupted. Implication: When this erratum occurs, the FPU Operand Data Pointer (FDP) may become corrupted. Workaround: This erratum will not occur with floating point exceptions masked.
Errata R F11. FSW May Not Be Completely Restored after Page Fault on FRSTOR or FLDENV Instructions Problem: If the FPU operating environment or FPU state (operating environment and register stack) being loaded by an FLDENV or FRSTOR instruction wraps around a 64-KB or 4-GB boundary and a page fault (#PF) or segment limit fault (#GP or #SS) occurs on the instruction near the wrap boundary, the upper byte of the FPU status word (FSW) might not be restored.
Errata R F14. Shutdown and IERR# May Result Due to a Machine Check Exception on a System with More Than One Logical Processor Problem: When a Machine Check Exception (MCE) occurs due to an internal error, all logical processors normally vector to the MCE handler. However, if one of the logical processors is in the “Waitfor-SIPI” state, that logical processor will not have an MCE handler and will shut down and assert IERR#.
Errata R F17. A Write to an APIC Registers Sometimes May Appear to Have Not Occurred Problem: With respect to the retirement of instructions, stores to the uncacheable memory-based APIC register space are handled in a non-synchronized way. For example if an instruction that masks the interrupt flag, e.g.
Errata R F20. Incorrect Debug Exception (#DB) May Occur When a Data Breakpoint Is Set on an FP Instruction Problem: The default Microcode Floating Point Event Handler routine executes a series of loads to obtain data about the FP instruction that is causing the FP event. If a data breakpoint is set on the instruction causing the FP event, the load in the microcode routine will trigger the data breakpoint resulting in a Debug Exception.
Errata R F23. Interactions between the Instruction Translation Lookaside Buffer (ITLB) and the Instruction Streaming Buffer May Cause Unpredictable Software Behavior Problem: Complex interactions within the instruction fetch/decode unit may make it possible for the processor to execute instructions from an internal streaming buffer containing stale or incorrect information.
Errata R F26. Data Breakpoints on the High Half of a Floating Point Line Split May Not Be Captured Problem: When a floating point load which splits a 64-byte cache line gets a floating point stack fault, and a data breakpoint register maps to the high line of the floating point load, internal boundary conditions exist that may prevent the data breakpoint from being captured. Implication: When this erratum occurs, a data breakpoint will not be captured. Workaround: None identified.
Errata R F30. Execution of IRET or INTn Instructions May Cause Unexpected System Behavior Problem: There is a small window of time, requiring alignment of many internal micro architectural events, during which the speculative execution of the IRET or INTn instructions in protected or IA-32e mode may result in unexpected software or system behavior. Implication: This erratum may result in unexpected instruction execution, events, interrupts or a system hang when the IRET instruction is executed.
Errata R F33. FXRSTOR May Not Restore Non-canonical Effective Addresses on Processors with Intel® Extended Memory 64 Technology (Intel® EM64T) Enabled Problem: If an x87 data instruction has been executed with a non-canonical effective address, FXSAVE may store that non-canonical FP Data Pointer (FDP) value into the save image. An FXRSTOR instruction executed with 64-bit operand size may signal a General Protection Fault (#GP) if the FDP or FP Instruction Pointer (FIP) is in non-canonical form.
Errata R F36. The IA32_MCi_STATUS MSR May Improperly Indicate that Additional MCA Information May Have Been Captured Problem: When a data parity error is detected and the bus queue is busy, the ADDRV and MISCV bits of the IA32_MCi_STATUS register may be asserted even though the contents of the IA32_MCi_ADDR and IA32_MCi_MISC MSRs were not properly captured.
Errata R F39. The Base of an LDT (Local Descriptor Table) Register May be Non-zero on a Processor Supporting Intel® Extended Memory 64 Technology (Intel® EM64T) Problem: In IA-32e mode of an Intel EM64T-enabled processor, the base of an LDT register may be nonzero. Implication: Due to this erratum, Intel EM64T-enabled systems may encounter unexpected behavior when accessing an LDT register using the null selector. There may be no #GP fault in response to this access. Workaround: None identified.
Errata R F41. Memory Ordering Failure May Occur with Snoop Filtering Third Party Agents after Issuing and Completing a BWIL (Bus Write Invalidate Line) or BLW (Bus Locked Write) Transaction Problem: Under limited circumstances, the processors may, after issuing and completing a BWIL or BLW transaction, retain data from the addressed cache line in shared state even though the specification requires complete invalidation.
Errata R F43. REP STOS/MOVS Instructions with RCX >=2^32 May Cause a System Hang Problem: In IA-32e mode using Intel EM64T-enabled processors, executing a repeating string instruction with the iteration count greater than or equal to 2^32 and a pending event may cause the REP STOS/MOVS instruction to live lock and hang. Implication: When this erratum occurs, the processor may live lock and result in a system hang. Intel has not observed this erratum with any commercially available software.
Errata R F46. A Data Access which Spans Both the Canonical and the Non-Canonical Address Space May Hang the System Problem: If a data access causes a page split across the canonical to non-canonical address space the processor may livelock which in turn would cause a system hang. Implication: When this erratum occurs, the processor may livelock, resulting in a system hang. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
Errata R F49. Incorrect Duty Cycle is Chosen when On-Demand Clock Modulation Is Enabled in a Processor Supporting Hyper-Threading Technology Problem: When a processor supporting Hyper-Threading Technology enables On-Demand Clock Modulation on both logical processors, the processor is expected to select the lowest duty cycle of the two potentially different values. When one logical processor enters the AUTOHALT state, the duty cycle implemented should be unaffected by the halted logical processor.
Errata R F52. Voltage and Frequency Transition May Not Occur if a Voltage Transition is Interrupted by a Warm Reset Problem: In an Enhanced Intel SpeedStep® Technology or Thermal Monitor 2 enabled system, if a voltage and frequency transition is interrupted by a warm reset and the next transition is to a higher voltage and frequency then that transition and all subsequent transitions will not be performed.
Errata R F55. The Processor May Issue Front Side Bus Transactions up to 6 Clocks after RESET# is Asserted Problem: The processor may issue transactions beyond the documented 3 Front Side Bus (FSB) clocks and up to 6 FSB clocks after RESET# is asserted in the case of a warm reset. A warm reset is where the chipset asserts RESET# when the system is running. Implication: The processor may issue transactions up to 6 FSB clocks after RESET# is asserted Workaround: None identified.
Errata R F58. CPUID Feature Flag Reports LAHF/SAHF as Unavailable however the Execution of LAHF/SAHF May Not Result in an Invalid Opcode Exception Problem: As described in the IA-32 Intel® Architecture Software Developer’s Manual, support for LAHF/SAHF instructions in 64-bit mode has been added to Intel EM64T processors.
Errata R F61. Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect Address Translations Problem: An external A20M# pin if enabled forces address bit 20 to be masked (forced to zero) to emulates real-address mode address wraparound at 1 megabyte.
Errata R F63. The IA32_MC0_STATUS and IA32_MC1_STATUS Overflow Bit is not set when Multiple Un-correctable Machine Check Errors Occur at the Same Time Problem: When two enabled MC0/MC1 un-correctable machine check errors are detected in the same bank in the same internal clock cycle, the highest priority error will be logged in IA32_MC0_STATUS / IA32_MC1_STATUS register, but the overflow bit may not be set.
Specification Changes R Specification Changes The Specification Changes listed in this section apply to the following documents: • Intel® Pentium® Processor Extreme Edition 840 Δ Datasheet • Intel® Pentium® D Processor 800 Δ Sequence Datasheet All Specification Changes will be incorporated into a future version of the appropriate processor documentation. There are no specification changes in this Specification Update revision.
Specification Clarifications R Specification Clarifications The Specification Clarifications listed in this section apply to the following documents: • Intel® Pentium® Processor Extreme Edition 840Δ Datasheet • Intel® Pentium® D Processor 800 Δ Sequence Datasheet All Specification Clarifications will be incorporated into a future version of the appropriate processor documentation.
Documentation Changes R Documentation Changes The Documentation Changes listed in this section apply to the following documents: • Intel® Pentium® Processor Extreme Edition 840∆ Datasheet • Intel® Pentium® D Processor 800 Δ Sequence Datasheet All Documentation Changes will be incorporated into a future version of the appropriate processor documentation.
